Commit Graph

753 Commits (0467ad41188031073cbbad1139a916e2439af2f1)

Author SHA1 Message Date
Nian Wu 0467ad4118 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-21 17:00:43 +08:00
Ben Skeggs e22225416a nouveau: support multiple channels per client (breaks drm interface) 2007-03-21 17:57:47 +11:00
Nian Wu 8398b99d8d Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-19 17:00:31 +08:00
Dave Airlie 26aba875e1 more whitespace issues 2007-03-19 08:56:24 +11:00
Dave Airlie 2463b03cb4 whitespace cleanup pending a kernel merge 2007-03-19 08:23:43 +11:00
Nian Wu df73975980 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-14 17:00:27 +08:00
Oliver McFadden 93f66af76a r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not
enough information is known about them to be sure as to what the values mean.
2007-03-13 14:48:01 +00:00
Nian Wu 80d0018bc0 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-13 17:00:31 +08:00
Oliver McFadden a90c2854a7 Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.
Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
2007-03-13 06:25:04 +00:00
Ben Skeggs 90f8c691a5 nouveau: make sure cmdbuf object gets destroyed 2007-03-13 14:55:54 +11:00
Ben Skeggs 1775202cf9 nouveau: associate all created objects with a channel + cleanups 2007-03-13 14:55:54 +11:00
Ben Skeggs 7e2bbe2954 nouveau: s/fifo/channel/ 2007-03-13 14:55:54 +11:00
Oliver McFadden 462a6ea4ca Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either
R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
2007-03-13 01:19:56 +00:00
Oliver McFadden 5667396e05 Guess another unknown register used for R300 pacification. 2007-03-13 00:50:05 +00:00
Nian Wu ab75d50d6c Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-12 09:03:40 +08:00
Patrice Mandin 0cd5c650d1 nouveau: PUT,GET, not 2xPUT 2007-03-11 14:02:40 +01:00
Nian Wu b369724077 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-07 16:01:50 -05:00
Thomas Hellstrom 6ffe94f008 Add via CX700. 2007-03-07 09:19:57 +01:00
Nian Wu 0a85c9fa02 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-05 09:01:45 -05:00
Dave Airlie 188a93c9df radeon: make PCI GART aperture size variable, but making table size variable
This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
Dave Airlie c9178c3d01 ati: make pcigart code able to handle variable size PCI GART aperture
This code doesn't enable a variable aperture it just modifies the codebase
to allow me fix it up later
2007-03-04 18:16:29 +11:00
Nian Wu 6c48b8e7ff Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-01 09:02:09 -05:00
Ben Skeggs 72caa48c82 nouveau: intrusive drm interface changes
graphics objects:
	- No longer takes flags/dmaobj parameters, requires some major changes
	  to the ddx to setup the object through the FIFO.  This change is
	  likely to cause breakages on some cards (tested on NV05,NV28,NV35,
	  NV40 and NV4E).
dma objects:
	- now takes a "class" parameter, not really used yet but we may need
	  it at some point.
	- parameters are checked, so clients can't randomly create DMA objects
	  pointing at whatever they feel like.
misc:
	- Added FB_SIZE/AGP_SIZE getparams
	- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
	- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
	  NOTIFICATION_PENDING.
2007-02-28 15:41:53 +11:00
Nian Wu df2fc3ec62 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-02-25 17:06:13 -08:00
Jakob Bornecrantz 9d8ba2d0d4 drm: remove unnecessary NULL checks, and fix some indents.. 2007-02-25 10:48:26 +11:00
Thomas Hellstrom e0f53e59be Simple fence object sample driver for via, based on idling the GPU.
Buffer object driver for via.
Some changes to buffer object driver callbacks.
Improve fence flushing.
2007-02-16 20:22:24 +01:00
Thomas Hellstrom 7766378d97 Initial support for fence object classes.
(Fence objects belonging to different command submission mechanisms).
2007-02-15 12:11:38 +01:00
Thomas Hellstrom a78f70faad Merge branch 'ttm-vram-0-1-branch' 2007-02-14 15:33:40 +01:00
Thomas Hellstrom 5c9a7b0f94 Remove an intel-specific hack and replace it with a fence driver callback. 2007-02-14 13:31:35 +01:00
Stephane Marchesin f524870184 nouveau: fix the build on big endian (thanks CyberFoxx) 2007-02-14 00:08:55 +01:00
B. Rathmann 59af900e4f nouveau: fix memory initialization with multiple cards. 2007-02-14 00:07:31 +01:00
Thomas Hellstrom e1460426b8 Bugzilla Bug #9457
Add refcounting of user waiters to the DRM hardware lock, so that we can use the
DRM_LOCK_CONT flag more conservatively.

Also add a kernel waiter refcount that if nonzero transfers the lock for the kernel context,
when it is released. This is useful when waiting for idle and can be used
for very simple fence object driver implementations for the new memory manager.

It also resolves the AIGLX startup deadlock for the sis and the via drivers.
i810, i830 still require that the hardware lock is really taken so the deadlock remains
for those two. I'm not sure about ffb. Anyone familiar with that code?
2007-02-13 20:47:30 +01:00
Wang Zhenyu 80095ffe01 i915: Add 965GM pci id update 2007-02-13 16:20:45 +08:00
Thomas Hellstrom abc14ddfb5 Update flags and comments. 2007-02-12 21:40:42 +01:00
Aapo Tahkola 130c39be3c Sync r300_reg.h from mesa driver. #10210 2007-02-11 10:24:14 +02:00
Michel Dänzer 4f795a05f1 Merge branch 'i915-pageflip' 2007-03-10 00:11:10 +01:00
Michel Dänzer d734992e6a i915: Only wait for pending flips before asynchronous flips again. 2007-03-10 00:10:49 +01:00
Michel Dänzer 0741064df4 i915: Do not wait for pending flips on both pipes at the same time.
The MI_WAIT_FOR_EVENT instruction does not support waiting for several events
at once, so this should fix the lockups with page flipping when both pipes are
enabled.
2007-03-09 16:39:13 +01:00
Ben Skeggs 1b3a6d4775 nouveau: remove a hack that's not needed since the last interface change. 2007-03-07 21:17:45 +11:00
Ben Skeggs 5bd0e52dba nouveau: ack PFIFO interrupts at PFIFO, not PMC. 2007-03-07 21:00:55 +11:00
Michel Dänzer a33859184a i915: Eliminate dev_priv->current_page.
Always use dev_priv->sarea_priv->pf_current_page directly. This allows clients
to modify it as well while they hold the HW lock, e.g. in order to sync pages
between pipes.
2007-02-28 17:48:56 +01:00
Michel Dänzer 074e10b384 i915: Only clean up page flipping when the last client goes away, not any one. 2007-02-28 15:57:08 +01:00
Michel Dänzer 1cdc1b6fba i915: Don't emit waits for pending flips before emitting synchronous flips.
The assumption is that synchronous flips are not isolated usually, and waiting
for all of them could result in stalling the pipeline for long periods of time.

Also use i915_emit_mi_flush() instead of an old-fashioned way to achieve the
same effect.
2007-02-28 15:23:19 +01:00
Michel Dänzer fd0fed3f1e i915: Fix test for synchronous flip affecting both pipes. 2007-02-28 12:33:56 +01:00
Michel Dänzer 1a0d890a42 i915: Add support for scheduled buffer swaps to be done as flips.
Unfortunately, emitting asynchronous flips during vertical blank results in
tearing. So we have to wait for the previous vertical blank and emit a
synchronous flip.
2007-02-22 17:21:18 +01:00
Michel Dänzer 5a40c043cc Add DRM_VBLANK_FLIP.
Used to request that a scheduled buffer swap be done as a flip instead of a
blit.
2007-02-22 17:19:30 +01:00
Michel Dänzer 6f89584e13 i915: Improved page flipping support, including triple buffering.
Pages are tracked independently on each pipe.

Bump the minor version for 3D clients to know page flipping is usable, and
bump driver date.
2007-02-19 15:08:40 +01:00
Michel Dänzer 34aa3393d0 i915: Page flipping enhancements.
Leave it to the client to wait for the flip to complete when necessary,
but wait for a previous flip to complete before emitting another one. This
should help avoid unnecessary stalling of the ring due to pending flips.

Call i915_do_cleanup_pageflip() unconditionally in preclose.
2007-02-19 15:08:40 +01:00
Michel Dänzer 078e430726 i915: Unify breadcrumb emission. 2007-02-19 15:08:40 +01:00
Thomas Hellstrom 53aee3122a I915 accelerated blit copy functional.
Fixed - to System memory copies are implemented by
flipping in a cache-coherent TTM,
blitting to it, and then flipping it out.
2007-02-09 16:36:53 +01:00