Commit Graph

647 Commits (1f1714cf3dd24ea4109722ea2b47bcf4725f27ea)

Author SHA1 Message Date
Ben Skeggs 1f1714cf3d nouveau: get c51 doing glxgears without the binary driver's help. 2007-01-06 18:05:21 +11:00
Ben Skeggs dbb0d979cc nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load. 2007-01-06 17:50:00 +11:00
Stephane Marchesin 528ab8ce40 nouveau: oops, we don't need OS_HAS_MTRR actually. 2007-01-05 20:59:45 +01:00
Stephane Marchesin d99c7c27e2 Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm 2007-01-05 20:50:46 +01:00
Stephane Marchesin 025f281bbf nouveau: Add an mtrr over the whole FB 2007-01-05 20:49:34 +01:00
Matthieu Castet 0f95ddc428 Merge branch 'master' of git+ssh://matc@git.freedesktop.org/git/mesa/drm/ 2007-01-05 19:41:12 +01:00
Matthieu Castet 9d167f1f4b Add basic pgraph context for nv10.
It only fake a context switch : pgraph state are not save/restored.
2007-01-05 19:40:11 +01:00
Stephane Marchesin f80659bc29 Cleanup the nv04 fifo code a bit. 2007-01-05 19:37:06 +01:00
Michel Dänzer 4fe2858f53 i915: Fix a DRM_ERROR that should be DRM_DEBUG.
It would clutter up the kernel output in a situation which is legitimate before
X.org 7.2 and handled correctly by the 3D driver.
2007-01-02 10:05:48 +01:00
Ben Skeggs 91855bb254 nouveau: oops, forgot to free RAMIN.. 2007-01-02 16:35:00 +11:00
Ben Skeggs 861017e6d5 nouveau: Hookup nv40_graph_init.
Now I can get 3D + working grctx switching on my NV40 without
the binary driver initialising the card first.  However, this
change also breaks 3D on my C51 even *with* the binary driver's
help.  So, it's likely that the weird voodoo is card-specific.
2007-01-02 15:56:10 +11:00
Ben Skeggs 41da9fd2e5 nouveau: Hook up grctx code for NV4x.
This is enough to get grctx switching going on my NV40 and C51 after
the binary driver has initialised the card first.

Bumping the drm patchlevel because the ddx needs some modifications to
have NV4x work at all with these changes.
2007-01-02 15:08:04 +11:00
Ben Skeggs 0e0d954584 nouveau: Add nv40-specific PGRAPH code, not hooked up yet. 2007-01-02 14:52:43 +11:00
Ben Skeggs 2c3bc69ba2 nouveau: Only clobber PFIFO if no channels are already alloc'd
With this change the GPU is responsible for doing the channel switch
itself.  This is needed for the upcoming NV4x PGRAPH context work as
we don't yet know enough to manually swap PGRAPH contexts.
2007-01-02 14:41:34 +11:00
Thomas Hellstrom a16a8a47cd Add some new via chipsets.
Disable 3D functionality and AGP DMA for chipsets with the DX9 3D engine.
2006-12-28 22:17:08 +01:00
Thomas Hellstrom 7859bd61d3 Leftover from previous commit. 2006-12-27 19:46:46 +01:00
Thomas Hellstrom 2980ec22a1 Allow for non-power-of-two texture pitch alignment. 2006-12-27 19:38:33 +01:00
Ben Skeggs c38ede0667 nouveau: return the *actual* type of memory alloc'd to userspace 2006-12-27 01:58:57 +11:00
Ben Skeggs 9e019df757 nouveau: Alloc cmdbuf for each channel individually 2006-12-26 23:30:26 +11:00
Ben Skeggs b7586ab539 nouveau: save/restore endianness flag on FIFO switch
This makes my G5 survive glxinfo and nouveau_demo - airlied
2006-12-21 17:47:10 +11:00
Thomas Hellstrom 3b47b27558 Some via PCI posting flushes. 2006-12-20 13:04:21 +01:00
Dave Airlie e5c4a26a29 Merge branch 'nouveau-1' 2006-12-20 10:30:16 +11:00
Dave Airlie 7458909bea fixup i915 return values from kernel 2006-12-19 21:48:18 +11:00
Dave Airlie 07635f26a9 fix comment in r128 2006-12-19 17:58:20 +11:00
Dave Airlie c52dea9a7d fix some sizes in sis_drv.h 2006-12-19 17:58:16 +11:00
Dave Airlie 8cc82c5033 remove inline from large function 2006-12-19 17:58:12 +11:00
Dave Airlie 13659357ad make a savage function static from kernel 2006-12-19 17:58:09 +11:00
Dave Airlie cb280ad3c0 fix missing DRM_ERR from kernel 2006-12-19 17:58:03 +11:00
Michel Dänzer aefc7a3443 Unify radeon offset checking.
Replace r300_check_offset() with generic radeon_check_offset(), which doesn't
reject valid offsets when the framebuffer area is at the very end of the card's
32 bit address space. Make radeon_check_and_fixup_offset() use
radeon_check_offset() as well.

This fixes https://bugs.freedesktop.org/show_bug.cgi?id=7697 .
2006-12-14 19:31:56 +01:00
Ben Skeggs 1a40f3318c Port remaining NV4 RAMIN access from the ddx into the drm.
Should fix lockups seen on NV4 cards.
2006-12-12 00:11:42 +11:00
Stephane Marchesin 30acb90a60 Merge the pciid work.
Add getparams for AGP and FB physical adresses.
Fix the MEM_ALLOC issue properly.
Fix context switches for nv44.
Change the DRM version to 0.0.1.
2006-12-03 10:02:54 +01:00
Michel Dänzer a97bb85c2a Unshare drm_drawable.c again for now.
The current version didn't build on BSD, where the new functionality isn't used
yet anyway. Whoever changes that will hopefully be able to make the OSes share
this file as well.
2006-12-01 10:46:21 +01:00
Ben Skeggs 80d75cf695 Use nouveau_mem.c to allocate RAMIN. 2006-11-30 10:31:42 +11:00
Ben Skeggs b1a9a76971 Wrap access to objects in RAMIN.
This will make it easier to support extra RAMIN in vram at a later point.
2006-11-30 08:35:42 +11:00
Matthieu Castet f48a7685bd For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.
When cleaning a fifo, we shouldn't assume everybody use nv40 ;)
Fill DMA_SUBROUTINE fill correct value.
2006-11-28 21:32:03 +01:00
Michel Dänzer ddcb994c3e i915_vblank_tasklet: Try harder to avoid tearing.
Previously, if there were several buffer swaps scheduled for the same vertical
blank, all but the first blit emitted stood a chance of exhibiting tearing. In
order to avoid this, split the blits along slices of each output top to bottom.
2006-11-27 11:32:33 +01:00
Stephane Marchesin 0a364be289 Merge branch 'nouveau-1' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm into nouveau-1 2006-11-21 23:32:58 +01:00
Ben Skeggs adf71cb29b Don't spam dmesg if PMC_INTSTAT is 0 2006-11-21 11:41:46 +11:00
Ben Skeggs 9ac7a8b0b4 Only return FIFO number if the FIFO is marked as in use.. 2006-11-18 10:09:29 +11:00
Ben Skeggs e9194dd1b0 Check some return vals, fixes a couple of oopses. 2006-11-18 10:03:45 +11:00
Ben Skeggs 18bba3fa29 Dump some useful info when a PGRAPH error occurs.
The "channel" detect doesn't work on my nv40, but the rest
seems to produce sane info.
2006-11-17 08:05:23 +11:00
Stephane Marchesin 5e7f58474d Merge branch 'nouveau-1' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm into nouveau-1 2006-11-16 14:47:52 +01:00
Ben Skeggs 2fd812f8ef Completely untested NV10/20/30 FIFO context switching changes. 2006-11-14 09:00:31 +11:00
Ben Skeggs 7002082944 Restructure initialisation a bit.
- Do important card init in firstopen
 - Give each channel it's own cmdbuf dma object
 - Move RAMHT config state to the same place as RAMRO/RAMFC
 - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-14 08:11:49 +11:00
Ben Skeggs 35bf8fb5cf Merge branch 'nouveau-1' of git+ssh://git.freedesktop.org/git/mesa/drm into nouveau-1 2006-11-14 04:52:08 +11:00
Ben Skeggs 9ef4bbc66c Hack around yet another "X restart borkage without nouveau.ko reload" problem.
On X init, PFIFO and PGRAPH are reset to defaults.  This causes the GPU to
loose the configuration done by the drm.  Perhaps a CARD_INIT ioctl a proper
solution to having this problem again in the future..
2006-11-14 04:51:13 +11:00
Stephane Marchesin 5a0cdf7db3 Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm into nouveau-1 2006-11-11 01:57:05 +01:00
Stephane Marchesin 1123ab0890 Fix memory detection on TNT2 M64/TNT2 vanta. 2006-11-10 02:18:38 +01:00
Eric Anholt 584acab6d6 Add drm_u64_t typedef on non-linux to fix libdrm build. 2006-11-07 09:36:40 -08:00
Dave Airlie f7affda35b drm: fixup page alignment on SAREA map on ppc64 2006-11-06 11:44:36 +11:00