Alex Deucher
e20c670a5a
LUT updates
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- Add gamma set for legacy chips
- Add 16 bpp gamma set
2008-08-14 09:19:03 +10:00
Alex Deucher
d4f9eaa55a
various cleanups
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- white space
- move i2c_lock to radeon_i2c.c
- enable tv dac on legacy
2008-08-14 09:19:03 +10:00
Alex Deucher
019745c417
Add legacy dac detect stubs
2008-08-14 09:19:03 +10:00
Alex Deucher
b6f5b8ec71
unify connector, i2c handling for atom and legacy
2008-08-14 09:19:02 +10:00
Alex Deucher
5f427e9aae
Brute force port of legacy crtc/encoder code
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- removed save/init/restore chain with set functions
2008-08-14 09:19:02 +10:00
Alex Deucher
7677c2dba5
on_each_cpu() compat fixup from krh
2008-08-14 09:19:02 +10:00
Dave Airlie
b167ccf10f
radeon: fix kernel_mm properly
2008-08-14 09:17:43 +10:00
Dave Airlie
0580785030
radeon: FEDORA: patch to make 3D driver work
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set gart buffers start
2008-08-14 09:15:28 +10:00
Dave Airlie
58df2fa0ec
radeon: remove debugging
2008-08-14 09:14:56 +10:00
Dave Airlie
b0ee12e6bb
radeon: use mm_enabled variable to denote memory manager running
2008-08-14 09:14:14 +10:00
Dave Airlie
18020e5e96
radeon: make buffer swap for older drivers work again on GEM
2008-08-14 09:12:36 +10:00
Dave Airlie
d59f41b8cf
radeon: add userspace call for mm support check
2008-08-14 09:11:15 +10:00
Dave Airlie
957c71ff52
radeon: FEDORA: add old DMA buffers on top of GEM
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This really shouldn't go upstream, it just lets me
run the old 3D driver on GEM setup system
2008-08-14 09:10:11 +10:00
Jesse Barnes
1c6abcefdc
i915: setup hardware status page if physical addrs are required
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Needed for the modesetting case where we initialize the ring at load time.
2008-08-13 11:39:22 -07:00
Jesse Barnes
b8724ae647
Merge branch 'modesetting-101' into modesetting-gem
2008-08-13 10:09:41 -07:00
Jesse Barnes
2f03ba4aad
Merge branch 'master' into modesetting-gem
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Conflicts:
libdrm/Makefile.am
libdrm/xf86drm.h
shared-core/i915_dma.c
shared-core/i915_irq.c
2008-08-13 10:08:02 -07:00
Thomas Hellstrom
af12ef4f6b
Don't call the vblank tasklet with irqs disabled.
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If a specific tasklet shares data with irq context,
it needs to take a private irq-blocking spinlock within
the tasklet itself.
2008-08-13 10:04:21 +02:00
Kristian Høgsberg
b0e6882946
[intel_bufmgr_gem] Fix flink buffer name caching ( #17085 , #17092 ).
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Store the global name in global_name, don't overwrite the gem_handle.
2008-08-12 22:22:55 -04:00
Jesse Barnes
085df6491e
Add error checking to framebuffer creation
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Make the Intel routine return an error if needed and make the core check for
it.
2008-08-12 18:23:58 -07:00
Jesse Barnes
e9648e9107
Export a generic dri_bo handle for use by clients
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We'll need something like this (either a handle field or a dri_bo_get_handle
function) for kernel mode setting to get at the handles.
2008-08-12 18:22:34 -07:00
Matthieu Herrb
966c783e96
libdrm: Allow build outside of source tree.
2008-08-11 10:48:47 -07:00
Dave Airlie
08faab27e5
drm_vm: fix for build on 2.6.22
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thanks to malc0 for pointing it out
2008-08-11 10:58:41 +10:00
Dave Airlie
280d415957
drm: add OS_HAS_GEM option.
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To build i915 driver pass OS_HAS_GEM=1 to make for now
2008-08-11 10:47:00 +10:00
Maarten Maathuis
9a2adc442a
NV50: minor changes
2008-08-09 19:50:00 +02:00
Maarten Maathuis
f79ed55462
NV50: enable hotplug irq
2008-08-09 19:47:06 +02:00
Maarten Maathuis
2b7feebb8a
NV50: call drm_sysfs_hotplug_event when appropriate
2008-08-09 19:33:32 +02:00
Dave Airlie
12e6a114cf
drm: TRUE/true
2008-08-09 17:19:16 +10:00
Eric Anholt
f7a9940715
Drop TTM interfaces from the userland library.
2008-08-08 15:57:47 -07:00
Eric Anholt
9e9d9b1741
Fix compile warning from check_aperture change.
2008-08-08 14:08:43 -07:00
Eric Anholt
e1b8e79796
Merge branch 'drm-gem'
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Conflicts:
shared-core/i915_dma.c
This brings in kernel support and userland interface for intel GEM.
2008-08-08 14:05:01 -07:00
Eric Anholt
46e9274e85
Replace the check_aperture API with one we can make thread-safe.
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While the bufmgr isn't thread-safe at the moment, we need it to be for shared
objects between contexts.
2008-08-08 13:58:29 -07:00
Stuart Bennett
0c47151a57
nouveau: wait for pgraph idle after loading or saving a context
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the nvidia driver does this, and it stops the error message appearing on nv40
2008-08-08 16:25:05 +01:00
Dave Airlie
c2184e450e
radeon: add initial support for legacy crtc/encoders.
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not all there yet
2008-08-08 16:04:45 +10:00
Jesse Barnes
8074b2e83d
Make modesetting-gem build with recent kernels
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Needed to merge in VM fault changes & pci_read_base API update.
2008-08-07 17:15:50 -07:00
Keith Packard
5968e061db
Make flink save the kernel-assigned name and return it instead of creating another name
2008-08-07 15:26:30 -07:00
Jesse Barnes
c7fb19e9b0
Merge branch 'drm-gem' into modesetting-gem
2008-08-07 14:02:04 -07:00
Keith Packard
ac20e14d23
Switch from shmem_getpage to read_mapping_page
2008-08-06 10:11:11 -07:00
Dave Airlie
8c042a0b05
radeon: fixup PCI GART table with GEM enabled
2008-08-06 15:59:31 +10:00
Dave Airlie
6435958673
radeon: just evict to TT not cached
2008-08-06 15:58:09 +10:00
Dave Airlie
a6c075fca6
drm: don't teardown things in modeset paths
2008-08-06 15:57:38 +10:00
Dave Airlie
04b5584c62
pcigart: fixup memset + remove wbinvd
2008-08-06 15:56:08 +10:00
Dave Airlie
513d4c3ff1
radeon: fix setting new memmap in right place
2008-08-06 10:21:20 +10:00
Keith Packard
dc0546c87f
[gem-intel] Retiring flush requests should clear flushed write_domains
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When i915_gem_retire_request has a flush which matches an object write
domain, clear the write domain. This will move the object to the inactive
list rather than the flushing list, avoiding trouble with objects left stuck
on the flushing list.
2008-08-05 16:06:40 -07:00
Keith Packard
ceb3d5e383
[gem-intel] Don't clear write_domain until flush completes
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In i915_gem_object_wait_rendering, if the object write domain is being
written by the GPU, the appropriate flushing commands are written to the
device and an additional request queued to mark that flush. Finally, the
function blocks on that new request.
The bug was that the write_domain in the object was cleared before the
function blocked.
If the wait is interrupted by a signal, the flushing commands may still be
pending. With the current write_domain information lost, the restarted
syscall will drop right through the write_domain test as that value was
lost, and so the function will not block at all. Oops.
Fixed by simply moving the write_domain clear until after the wait_request
succeeds. Note that the restarted system call will generate an additional
flush sequence and request, but that should be 'harmless', aside from a
slight performance impact.
Someday we'll track flushing more accurately and clear write_domains more
efficiently, but for now, this should suffice.
This bug was discovered in the 2d gem development by running x11perf
-copypixwin500 and noticing that the window got cleared accidentally.
2008-08-05 14:44:53 -07:00
Keith Packard
8e41ce17b4
Expose pin/unpin/set_tiling/flink APIs
2008-08-04 23:34:16 -07:00
Dave Airlie
4748fbcbd7
radeon: fix blit due to registers wrong
2008-08-05 11:36:37 +10:00
Dave Airlie
fd75c02ddd
drm: finish bo after lastclose
2008-08-04 14:59:49 +10:00
Dave Airlie
aa8e15f8b5
radeon: add userspace mm enable switch
2008-08-04 14:59:17 +10:00
Dave Airlie
29649ddede
radeon: don't use ring if cp not going
2008-08-04 14:56:08 +10:00
Dave Airlie
dff8485151
drm: remove unused types
2008-08-04 14:55:12 +10:00