Commit Graph

17 Commits (33f0009de5534b3e0ad886dfe0414f982644aade)

Author SHA1 Message Date
Matt Roper 98794e2a0d lib: sync i915_pciids.h with kernel
This synchronizes with kernel commit 7835303982d1 ("drm/i915/mtl: Add
MeteorLake PCI IDs") to bring in the missing PCI IDs for several recent
platforms.

These days adding PCI IDs to libdrm doesn't really matter for real-world
system usage.  However there are still a few driver testing situations
where they're needed (such as the IGT dma-buf tests that still rely on
libdrm's bufmgr code).  At some point we should probably break that
final IGT dependency on libdrm so that these PCI ID resyncs won't be
necessary anymore, but that hasn't happened yet.

References: https://gitlab.freedesktop.org/drm/intel/-/issues/5416
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2022-08-03 22:48:27 +00:00
Tejas Upadhyay d95b12e7e3 intel: Add support for RPLP
Add RPLP platform support and PCIIDs

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com>
2022-04-21 23:04:33 +05:30
Tejas Upadhyay 440e2d7a34 intel: Add support for ADL-N
Add ADL-N platform support and PCIIDs

Align with kernel commit:
7e28d0b26759 ("drm/i915/adl-n: Enable ADL-N platform")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
2021-12-21 13:54:52 +00:00
Raviteja Goud Talla 3d8e59ce01 intel: sync i915_pciids.h with kernel
Align with kernel commit:

52407c220c44c ("drm/i915/rpl-s: Add PCI IDS for Raptor Lake S")

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2021-12-16 18:20:31 +05:30
José Roberto de Souza 02dd464bf6 intel: Sync pci ids
Sync libdrm with kernel, a new DG1 pci was added.
Commit 5f0d4214938d ("drm/i915/dg1: Add new PCI id")

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
2021-09-23 21:40:58 +00:00
Tejas Upadhyay a7892962e1 intel: sync ADL-S PCI IDs with kernel
Align with kernel commits:

c79b846f892d ("drm/i915/adl_s: Update ADL-S PCI IDs")
3f50033dd88a ("drm/i915/adl_s: ADL-S platform Update PCI ids for Mobile BGA")

Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
2021-08-24 12:49:19 +05:30
Tejas Upadhyay 4c8365183e intel: Add support for ADLP
Add ADLP platform support and PCIIDs

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Pankaj Bharadiya <pankaj.laxminarayan.bharadiya@intel.com>
Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
2021-05-20 12:01:25 +00:00
Tejas Upadhyay 9086ff9daf intel: sync i915_pciids.h with kernel
Align with kernel commits:

0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
04057a1afc75 ("drm/i915: Sort EHL/JSL PCI IDs")
0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")
605f9c290c1a ("drm/i915: Sort ICL PCI IDs")
514dc424ce4f ("drm/i915: Sort CNL PCI IDs")
32d4ec9a1681 ("drm/i915: Sort CFL PCI IDs")
df3478af1d73 ("drm/i915: Sort CML PCI IDs")
cd988984cbea ("drm/i915: Sort KBL PCI IDs")
b04d36f73771 ("drm/i915: Sort SKL PCI IDs")
9c0b2d30441b ("drm/i915: Sort HSW PCI IDs")
79033a0a7898 ("drm/i915: Ocd the HSW PCI ID hex numbers")
cfb3db8fdae2 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
03e399020cd2 ("drm/i915: Add SKL GT1.5 PCI IDs")
812f044df08c ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
194909a32aed ("drm/i915: Reclassify SKL 0x192a as GT3")
82e84284ab7d ("drm/i915: Update Haswell PCI IDs")
24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
b50b7991b739 ("drm/i915/dg1: add more PCI ids")
d452bd091e16 ("drm/i915: break TGL pci-ids in GT 1 & 2")
f2bde2546b81 ("drm/i915: Remove dubious Valleyview PCI IDs")
0883d63b19bb ("drm/i915/adl_s: Add ADL-S platform info and PCI ids")
04057a1afc75 ("drm/i915: Sort EHL/JSL PCI IDs")
0e8e272f1368 ("drm/i915/ehl: Remove invalid PCI ID")
605f9c290c1a ("drm/i915: Sort ICL PCI IDs")
514dc424ce4f ("drm/i915: Sort CNL PCI IDs")
32d4ec9a1681 ("drm/i915: Sort CFL PCI IDs")
df3478af1d73 ("drm/i915: Sort CML PCI IDs")
cd988984cbea ("drm/i915: Sort KBL PCI IDs")
b04d36f73771 ("drm/i915: Sort SKL PCI IDs")
9c0b2d30441b ("drm/i915: Sort HSW PCI IDs")
79033a0a7898 ("drm/i915: Ocd the HSW PCI ID hex numbers")
cfb3db8fdae2 ("drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments")
03e399020cd2 ("drm/i915: Add SKL GT1.5 PCI IDs")
812f044df08c ("drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT")
194909a32aed ("drm/i915: Reclassify SKL 0x192a as GT3")
82e84284ab7d ("drm/i915: Update Haswell PCI IDs")
24ea098b7c0d ("drm/i915/jsl: Split EHL/JSL platform info and PCI ids")
b50b7991b739 ("drm/i915/dg1: add more PCI ids")
d452bd091e16 ("drm/i915: break TGL pci-ids in GT 1 & 2")

Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Reviewed-by: Landwerlin, Lionel G <lionel.g.landwerlin@intel.com>
2021-02-18 10:12:28 +00:00
Adam Miszczak a9591d66fe intel: sync i915_pciids.h with kernel
Add DG1 and clean-up VLV PCI IDs.

Align with kernel commits:
f2bde2546b81 ("drm/i915: Remove dubious Valleyview PCI IDs")
fd38cdb81105 ("drm/i915/dg1: Add DG1 PCI IDs")

Signed-off-by: Adam Miszczak <adam.miszczak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2020-08-27 09:06:04 +00:00
José Roberto de Souza 669e1087ab intel: sync i915_pciids.h with kernel
Two new patches landed in kernel adding new PCI ids:
123f62de419f ("drm/i915/rkl: Add RKL platform info and PCI ids")
52797a8e8529 ("drm/i915/ehl: Add new PCI ids")

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
2020-07-08 10:44:53 -07:00
Swathi Dhanavanthri bb4e154d3d intel: sync i915_pciids.h with kernel
Changes:
3882581753d1 ("drm/i915/tgl: Add new PCI IDs to TGL")

Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Reviewed-by: Timo Aaltonen <timo.aaltonen@canonical.com>
2020-03-23 13:51:19 +02:00
José Roberto de Souza 4c31d1181b intel: sync i915_pciids.h with kernel
Changes:
651cc835d5f6 ("drm/i915: Add new EHL/JSL PCI ids")
b6a8781a447c ("drm/i915/cml: Remove unsupport PCI ID")
8717c6b7414f ("drm/i915/cml: Separate U series pci id from origianl list.")

v2: added the latest CML changes

Cc: James Ausmus <james.ausmus@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-12-17 13:27:46 -08:00
Anusha Srivatsa 10cd9c3da8 intel: sync i915_pciids.h with kernel
Add the new CML PCI IDS.

Align with kernel commit:
bfc4c359b2822 ("drm/i915/cml: Add Missing PCI IDs")

This is in sync with kernel header as of:
0747590267e7 ("drm-tip: 2019y-08m-30d-18h-03m-18s UTC integration manifest")

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
2019-09-06 13:12:14 -07:00
Lucas De Marchi 3bda60fd14 intel: sync i915_pciids.h with kernel
Straight copy from the kernel file, aligned with drm-intel-next-queued
commit cb823ed9915b ("drm/i915/gt: Use intel_gt as the primary object
for handling resets")

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2019-07-29 16:55:40 -07:00
Anusha ae836decb4 intel: sync i915_pciids.h with kernel
Add CML and EHL PCI IDs, and one more for ICL. This is in sync with
kernel header as of b024ab9b2d3a ("drm/i915/bios: iterate over child
devices to initialize ddi_port_info")

Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
2019-03-25 14:34:13 -07:00
Rodrigo Vivi 70a1ae89be intel: sync i915_pciids.h with kernel
Straight copy from the kernel file.

Add more PCI Device IDs for Coffee Lake, Ice Lake,
and Amber Lake. It also include a reorg on Whiskey Lake IDs.

Align with kernel commits:

5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.")
03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake")
c0c46ca461f1 ("drm/i915/aml: Add new Amber Lake PCI ID")
c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs")

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-02-04 10:45:53 -08:00
Lucas De Marchi 4e81d4f9c9 intel: add generic functions to check PCI ID
This will allow platforms to reuse kernel IDs instead of manually
keeping them in sync. In most of the cases we only need to extend
IS_9XX().  Current platforms that fit this requirement can be ported
over to use this macro. Right now it's a nop since it doesn't have any
PCI ID added.

The i915_pciids.h header is in sync with kernel tree on
drm-tip 2018y-08m-20d-21h-41m-11s.

v2: - move to a separate .c so we can have the array in a single
      compilation unit
    - use a single array for all gens
    - add real functions to get or check gen by pciid
    - define our own pci device struct rather than inherit the one
      kernel uses: we can throw away most of the fields

v3: - add comment to keep ids sorted by gen
    - remove misleading comment about all gens

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-09-05 16:14:04 -07:00