26aba875e1
more whitespace issues
2007-03-19 08:56:24 +11:00
c991f8e049
cleanup ioctl expansion code
2007-03-19 08:46:39 +11:00
a2e3bae8e2
oops missing else
2007-03-19 08:46:25 +11:00
bbb6fc9307
make drm fops const from kernel
2007-03-19 08:36:01 +11:00
483f6a113d
use ARRAY_SIZE
2007-03-19 08:32:25 +11:00
2d7ecb8422
more tab/space conversion
2007-03-19 08:29:07 +11:00
2463b03cb4
whitespace cleanup pending a kernel merge
2007-03-19 08:23:43 +11:00
6c4428d40c
clean up more of inline functions agp_remap/drm_lookup_map
2007-03-19 08:09:21 +11:00
27197d7836
deinline agp_remap along lines of kernel
2007-03-18 21:45:07 +11:00
c4808e206b
remove drm_lookup_map unused now
2007-03-18 21:42:48 +11:00
df73975980
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-14 17:00:27 +08:00
93f66af76a
r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not
...
enough information is known about them to be sure as to what the values mean.
2007-03-13 14:48:01 +00:00
80d0018bc0
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-13 17:00:31 +08:00
a90c2854a7
Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.
...
Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
2007-03-13 06:25:04 +00:00
90f8c691a5
nouveau: make sure cmdbuf object gets destroyed
2007-03-13 14:55:54 +11:00
1775202cf9
nouveau: associate all created objects with a channel + cleanups
2007-03-13 14:55:54 +11:00
7e2bbe2954
nouveau: s/fifo/channel/
2007-03-13 14:55:54 +11:00
462a6ea4ca
Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either
...
R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
2007-03-13 01:19:56 +00:00
5667396e05
Guess another unknown register used for R300 pacification.
2007-03-13 00:50:05 +00:00
ab75d50d6c
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-12 09:03:40 +08:00
0cd5c650d1
nouveau: PUT,GET, not 2xPUT
2007-03-11 14:02:40 +01:00
b369724077
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-07 16:01:50 -05:00
6ffe94f008
Add via CX700.
2007-03-07 09:19:57 +01:00
0a85c9fa02
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-05 09:01:45 -05:00
188a93c9df
radeon: make PCI GART aperture size variable, but making table size variable
...
This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
c9178c3d01
ati: make pcigart code able to handle variable size PCI GART aperture
...
This code doesn't enable a variable aperture it just modifies the codebase
to allow me fix it up later
2007-03-04 18:16:29 +11:00
6c48b8e7ff
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-01 09:02:09 -05:00
0bbbb46650
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-02-28 09:00:12 -05:00
72caa48c82
nouveau: intrusive drm interface changes
...
graphics objects:
- No longer takes flags/dmaobj parameters, requires some major changes
to the ddx to setup the object through the FIFO. This change is
likely to cause breakages on some cards (tested on NV05,NV28,NV35,
NV40 and NV4E).
dma objects:
- now takes a "class" parameter, not really used yet but we may need
it at some point.
- parameters are checked, so clients can't randomly create DMA objects
pointing at whatever they feel like.
misc:
- Added FB_SIZE/AGP_SIZE getparams
- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
NOTIFICATION_PENDING.
2007-02-28 15:41:53 +11:00
7c3aeafe75
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-02-27 14:42:26 -05:00
6a51da7325
Fix Alpha domain/bus issue
2007-02-27 08:56:20 +00:00
80468e7532
Fix build for 2.6.21-rc1.
...
The vm subsystem of 2.6.21 is fully compatible with the buffer object
vm code.
2007-02-26 18:17:54 +01:00
df2fc3ec62
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-02-25 17:06:13 -08:00
9d8ba2d0d4
drm: remove unnecessary NULL checks, and fix some indents..
2007-02-25 10:48:26 +11:00
2b7a9afa09
Some fencing cleanup.
2007-02-22 17:04:20 +01:00
a253de2fcf
drm: remove last usage of VM_OFFSET
2007-02-18 17:59:40 +11:00
6d8ed5aedd
Leftover files from previous commit.
2007-02-16 20:25:26 +01:00
e0f53e59be
Simple fence object sample driver for via, based on idling the GPU.
...
Buffer object driver for via.
Some changes to buffer object driver callbacks.
Improve fence flushing.
2007-02-16 20:22:24 +01:00
7766378d97
Initial support for fence object classes.
...
(Fence objects belonging to different command submission mechanisms).
2007-02-15 12:11:38 +01:00
7803977aa9
Fix build against older kernels.
2007-02-15 09:26:16 +01:00
a78f70faad
Merge branch 'ttm-vram-0-1-branch'
2007-02-14 15:33:40 +01:00
35eb12d8bf
Fix multiple spinlock unlocking
2007-02-14 15:32:08 +01:00
1345076c8f
Rename drm_ttm.h to drm_objects.h
...
Fix up some header incompatibilities in drm_fence.c caused by the previous
commit.
2007-02-14 14:10:10 +01:00
8ffc1844b0
Move fence- and buffer-object related header stuff to drm_ttm.h
2007-02-14 14:05:40 +01:00
5c9a7b0f94
Remove an intel-specific hack and replace it with a fence driver callback.
2007-02-14 13:31:35 +01:00
04760563b8
Set the drm bus map type for each buffer object memory type.
2007-02-14 12:39:02 +01:00
7bcb62b45d
Rework buffer object vm code to use nopfn() for kernels >= 2.6.19.
2007-02-14 10:49:37 +01:00
f524870184
nouveau: fix the build on big endian (thanks CyberFoxx)
2007-02-14 00:08:55 +01:00
59af900e4f
nouveau: fix memory initialization with multiple cards.
2007-02-14 00:07:31 +01:00
6b289db054
Remove debug printout.
2007-02-13 20:47:30 +01:00
Dave Airlie
Nian Wu
Oliver McFadden
Ben Skeggs
Patrice Mandin
Thomas Hellstrom
Nian Wu
Jay Estabrook
Nian Wu
Jakob Bornecrantz
Michel Dänzer
Stephane Marchesin
B. Rathmann