Commit Graph

333 Commits (35affe89d5f617a972b1cfee00c51cbe9e7c64a2)

Author SHA1 Message Date
Emil Velikov 4dfa458979 Revert "libdrm: intel/Android.mk: Filter libdrm_intel library requirements on x86/x86_64"
This reverts commit ed07718ae7.

The commit added a guard since libpciaccess may be missing on some
setups. As of last commit there are no traces of the project, from
Android POV.

Hence, we can revert this workaround - which caused similar breakage to
the one it's trying to fix. This time in Mesa.

Cc: Rob Herring <rob.herring@linaro.org>
Acked-by: John Stultz <john.stultz@linaro.org>
2018-03-28 17:08:32 +01:00
Tomasz Figa bb0fd5f3b3 intel: Do not use libpciaccess on Android
This patch makes the code not rely anymore on libpciaccess when compiled
for Android to eliminate ioperm() and iopl() syscalls required by that
library. As a side effect, the mappable aperture size is hardcoded to 64
MiB on Android, however nothing seems to rely on this value anyway, as
checked be grepping relevant code in drm_gralloc and Mesa.

Cc: Rob Herring <rob.herring@linaro.org>
Signed-off-by: Tomasz Figa <tfiga@google.com>
[Emil Velikov: rebase against master. add missing __func__, Eric]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: John Stultz <john.stultz@linaro.org>
2018-03-28 17:08:32 +01:00
Eric Engestrom 0926f0af54 meson,configure: include config.h automatically
This will prevent any more missing `#include "config.h"` bug, at the
cost of having to recompile some files that didn't need to be when
changing build options.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-03-20 18:19:26 +00:00
Eric Engestrom 1a44bbae73 meson,configure: always define HAVE_OPEN_MEMSTREAM
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-03-20 14:30:27 +00:00
John Stultz ed07718ae7 libdrm: intel/Android.mk: Filter libdrm_intel library requirements on x86/x86_64
When building AOSP after updating libdrm project to the
freedesktop/master branch, I've seen the following build errors:

external/libdrm/intel/Android.mk: error: libdrm_intel
(SHARED_LIBRARIES android-arm64) missing libpciaccess
(SHARED_LIBRARIES android-arm64) You can set
ALLOW_MISSING_DEPENDENCIES=true in your environment if this is
intentional, but that may defer real problems until later in the
build.

Using ALLOW_MISSING_DEPENDENCIES=true when building allows
things to function properly, but is not ideal.

So basically, while I'm not including the libdrm_intel package
into the build, just the fact that the Android.mk file references
libpciaccess which isn't a repo included in AOSP causes the build
failure.

So it seems we need some sort of conditional filter in the
Android.mk to skip over it if we're not building for intel.

Cc: Chad Versace <chad.versace@linux.intel.com>
Cc: Marissa Wall <marissaw@google.com>
Cc: Sean Paul <seanpaul@google.com>
Cc: Dan Willemsen <dwillemsen@google.com>
Cc: Tomasz Figa <tfiga@google.com>
Cc: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
2018-03-18 23:18:36 -05:00
Eric Engestrom 5236de6cc1 meson: use pkg-config to detect libatomic_ops
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-03-09 17:12:02 +00:00
Rodrigo Vivi 7b12381723 intel/intel_chipset.h: Sync Cannonlake IDs.
Let's sync CNL ids with Spec and kernel.

Sync with kernel commit '3f43031b1693 ("drm/i915/cnl:
Add Cannonlake PCI IDs for another SKU.")' and
commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")'

Cc: James Ausmus <james.ausmus@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-03-05 15:13:05 -08:00
Heiko Becker 4f08bfe96d *-symbol-check: Don't hard-code nm executable
Helpful if your nm executable has a prefix based on the
architecture, for example.

Signed-off-by: Heiko Becker <heirecka@exherbo.org>
Cc: Timo Gurr <timo.gurr@gmail.com>
[Eric: v2: rebase and add Meson support]
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-02-23 17:53:08 +00:00
Eric Engestrom 1d7bbf8520 always define HAVE_VALGRIND
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-01-29 15:41:52 +00:00
Dylan Baker 5f7deb5078 Add meson build system
This patch adds a complete meson build system, including tests and
install. It has the necessary hooks to allow it be used as a subproject
for other meson based builds such as mesa.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-and-tested-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2018-01-12 09:40:48 -08:00
Anuj Phogat d3cb588315 intel: Add more Coffeelake PCI IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-01-11 10:29:02 -08:00
Anuj Phogat 7c71188610 intel: Change a KBL pci id to GT2 from GT1.5
See Mesa commit 9c588ff

Cc: Matt Turner <mattst88@gmail.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-09-21 14:40:41 -07:00
Rodrigo Vivi 68da7812fc intel/intel_chipset: Move IS_9XX below IS_GEN10.
No functional change. Just organizing the code
so it gets clear for future platforms.

Paulo deserves credits becuase he was the one
that just noticed this IS_9XX was in the wrong position
after CNL patches got introduced.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30 14:25:24 -07:00
Paulo Zanoni 3095cc8eab intel: add GEN10 to IS_9XX.
As far as I understand, IS_9XX should return true for it.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30 08:30:48 -07:00
Ben Widawsky 5c490bd685 intel/gen10: Add missed gen10 stuff
This got lost on rebase, I believe

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30 08:30:43 -07:00
Rodrigo Vivi 80201d7067 intel: Add Cannonlake PCI IDs for Y-skus.
By the Spec all CNL Y skus are 2+2, i.e. GT2.

This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")

v2: Add kernel commit id for reference.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-06-30 08:30:28 -07:00
Rodrigo Vivi 6b624bf3c3 intel: Add Cannonlake PCI IDs for U-skus.
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.

This is a copy of merged i915's
commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")

v2: Remove PCI IDs for SKU not mentioned in spec.
v3: Add kernel commit id for reference.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-06-30 08:30:08 -07:00
Anusha Srivatsa 4c98652cb5 intel: PCI Ids for U SKU in CFL
Add the PCI IDs for U SKU IN CFL by following the spec.

v2: Update IDs

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29 10:51:29 -07:00
Anusha Srivatsa 2b48faf30e intel: PCI Ids for H SKU in CFL
Add the PCI IDs for H SKU IN CFL by following the spec.

v2: Update IDs

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29 10:51:15 -07:00
Anusha Srivatsa 0733f376ae intel: PCI Ids for S SKU in CFL
Add the PCI IDs for S SKU IN CFL by following the spec.

v2: Update IDs.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29 10:50:54 -07:00
Eric Engestrom 3f1df25e0b intel: remove dead code
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2017-04-10 17:17:12 +01:00
Chris Wilson 19c4cfc549 intel: Add handle to hashtable before freeing along an error path
drm_intel_gem_bo_free() unconditionally attempts to remove the handle
from the hashtable. This goes horribly wrong if we haven't already added
the bo to the hashtable.

Reported-by: Michael Thayer <michael.thayer@oracle.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-03-08 21:03:22 +00:00
Thomas Hindoe Paaboel Andersen 5ee9cb4b4b intel: avoid null pointer dereference
Move the dereference after the null check.
Fixes: 028715ee70 ("intel: Avoid the need for most overflow
                              checks by using a scratch page.")
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-02-28 13:38:09 +00:00
Chris Wilson ec80fd36a7 intel: Move 48b support to bo_gem->kflags
Another boolean that can be set and used along side the other execobject
flags.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-02-11 11:05:42 +00:00
Chris Wilson e0f05b2fad intel: Move is_softpin to obj->kflags
Use obj->kflags to set EXEC_OBJECT_PINNED when the object is softpinned,
and so remember to clear the softpin status when the object is freed
(and reused).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-02-11 11:02:06 +00:00
Dave Airlie 0ad0c12fd3 intel: fix make distcheck
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-28 11:13:59 +10:00
Chris Wilson dfd536c60d intel: Export a function to re-enable implicit synchronisation
Implicit synchronisation is the default behaviour of the kernel when
rendering with an execobject. It may be disabled with
drm_intel_gem_bo_disable_implicit_sync(), and then to restore it use
drm_intel_gem_bo_enable_implicit_sync().

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27 20:25:04 +00:00
Chris Wilson 22cfd04311 intel: Clear execobject flags before preserving object in reuse cache
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27 20:20:30 +00:00
Chris Wilson c4b00767a7 intel: Support passing of explicit fencing from execbuf
Allow the caller to pass in an fd to an array of fences to control
serialisation of the execbuf in the kernel and on the GPU, and in return
allow creation of a fence fd for signaling the completion (and flushing)
of the batch. When the returned fence is signaled, all writes to the
buffers inside the batch will be complete and coherent from the cpu, or
other consumers. The return fence is a sync_file object and can be
passed to other users (such as atomic modesetting, or other drivers).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27 20:00:38 +00:00
Chris Wilson 1bd35da961 intel: Allow the client to control implicit synchronisation
The kernel allows implicit synchronisation to be disabled on individual
buffers. Use at your own risk.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27 20:00:38 +00:00
Emil Velikov 03d2e91d00 android: introduce Android.common.mk to reduce boilerplate
... across the makefiles. Currently this isn't much but that will change
shortly.

As an added bonus this fixes all present and future cases where we've
forgotten to strip out the headers from LOCAL_SRC_FILES.

In a couple of cases (the tests) we start setting
LOCAL_EXPORT_C_INCLUDE_DIRS, which shouldn't be an issue.

Cc: Chih-Wei Huang <cwhuang@android-x86.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
2017-01-27 15:48:16 +00:00
Emil Velikov de5b41ef5a android: remove LOCAL_MODULE_TAGS := optional tag
Seems to be the default option since ~2009 with commit 2f31293ba78 "auto
import from //branches/cupcake/...@137197". Fleshed out from a larger
commit in the AOSP repo/fork.

Cc: Dan Willemsen <dwillemsen@google.com>
Cc: Chih-Wei Huang <cwhuang@android-x86.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
2017-01-27 15:47:13 +00:00
Dongwon Kim 44f220ad62 intel: update global_name before HASH_ADD
bo->global_name should be updated first before a hash value
for the entry is calculated with it by HASH_ADD macro.

Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-15 20:15:37 +00:00
Grazvydas Ignotas 1924b6704a libdrm: random typo fixes
Just some trivial boring typo fixes all over the tree.
READMEs and comments only.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-11-22 13:54:31 +00:00
Michel Dänzer 911280cb4a intel: Add drm_intel_gem_context_get_id to intel-symbols-check
Fixes make check. Trivial.
2016-11-22 15:48:12 +09:00
Robert Bragg 770f6bc424 intel: Add a getter for the intel_context ctx_id
Exposing the u32 context ID makes it possible to define new drm kernel
interfaces based on the same IDs that e.g. execbuf uses to identify a
gem context, that aren't themselves abstracted by libdrm but need to be
used by libdrm/drm_intel_context based clients such as (parts of) i-g-t
or Mesa.

For example this can be used to configure an i915-perf stream to collect
metrics for a specific context.

v2: s/drm_intel_gem_context_get_context_id/drm_intel_gem_context_get_id/

Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
2016-11-21 16:33:55 +00:00
Ben Widawsky 3e81f8b7b9 intel: Add Geminilake PCI IDs
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2016-11-18 15:57:55 -08:00
Matt Turner 51002c0440 intel: Add uthash.h to Makefile.sources. 2016-11-14 10:40:59 -08:00
Neil Roberts 319108f947 intel: Allow some codenames in INTEL_DEVID_OVERRIDE
As well as allowing a hexadecimal PCI ID number, the
INTEL_DEVID_OVERRIDE environment variable can now contain one of a few
short codenames. The codenames are stored in a small table to map them
to a corresponding PCI ID. This makes it easier to use without having
to look up the PCI IDs manually.

The PCI IDs used are the same as those chosen for the -p option of
run.c in shader-db but SKL has been added as well.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-11-14 10:40:58 -08:00
Chris Wilson fe4579e263 intel: Look prime handle up in handle hash table
A slightly confused copy'n'paste from the open path where we pass in
handle but use it as a global name, in the prime handle-from-fd pass we
pass in handle and do mean handle!

References: https://bugs.freedesktop.org/show_bug.cgi?id=98416
Fixes: 2f23bf1b7b89 ("intel: Migrate handle/name lookups from linear lists...")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-10-24 21:19:52 +01:00
Michel Dänzer ec39fe07e7 intel: Add new symbols to intel-symbol-check
Fixes make check.

Trivial.
2016-10-24 11:14:36 +09:00
Chris Wilson 9e24d0c54b intel: Migrate handle/name lookups from linear lists to hashtables
Walking a linear list to find a matching PRIME handle or flinked name
does not scale and becomes a major burden with just a few objects.
That said, the fixed size hash is not much better, it just buckets the
look into a few separate chains rather than one long one.

References: https://bugs.freedesktop.org/show_bug.cgi?id=94631
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-10-22 09:32:54 +01:00
Chris Wilson 455e9b4917 intel: Export raw GEM mmap interfaces
Export a set of interfaces to allow the caller to have precise control
over mapping the buffer - but still provide caching of the mmaps between
callers.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-10-22 09:32:54 +01:00
Michel Dänzer 2d00869599 intel: Add new symbols to intel-symbol-check
Fixes make check.

Trivial.
2016-09-08 15:19:49 +09:00
Yang Rong 98887140e3 intel: Export pooled EU and min no. of eus in a pool.
Update kernel interface with new I915_GETPARAM ioctl entries for
pooled EU and min no. of eus in a pool. Add a wrapping function
for each parameter. Userspace drivers need these values when decide
the thread count. This kernel enabled pooled eu by default for BXT
and for fused down 2x6 parts it is advised to turn it off.

But there is another HW issue in these parts (fused
down 2x6 parts) before C0 that requires Pooled EU to be enabled as a
workaround. In this case the pool configuration changes depending upon
which subslice is disabled and the no. of eus in a pool is different,
So userspace need to know min no. of eus in a pool.

V2: use return value as the query results.
    ret < 0 when error, ret = 0 when not support, and ret > 0 indicate
    query results.(Chris)
V3: Correct V2 errors.

Signed-off-by: Yang Rong <rong.r.yang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2016-09-07 13:50:23 +01:00
Andreas Boll a5446775f2 automake: Don't include Android Makefiles in the release tarball
Currently only some Android Makefiles are included in the release tarball.
To be more consistent one could either add the remaining files or don't
ship Android Makefiles altogether.

According to Emil the Android folk doesn't use our release tarballs.
Thus it makes sense to remove those files from distribution which also
means less work for maintenance in the future.

Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2016-07-23 09:45:53 +02:00
Rob Herring d342cd34ac Android: strip out header files from sources list
AOSP master now errors if LOCAL_SRC_FILES contains headers, so filter
out header files from the source lists.

Signed-off-by: Rob Herring <robh@kernel.org>
2016-07-06 16:58:38 +01:00
Rodrigo Vivi 7996a8707e intel: Removing PCI IDs that are no longer listed as Kabylake.
This is unusual. Usually IDs listed on early stages of platform
definition are kept there as reserved for later use.

However these IDs here are not listed anymore in any of steppings
and devices IDs tables for Kabylake on configurations overview
section of BSpec.

So it is better removing them before they become used in any
other future platform.

v2: Rebase.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2016-06-29 10:23:37 -07:00
Rodrigo Vivi 22b6e33fe2 intel: Add more Kabylake PCI IDs.
The spec has been updated adding new PCI IDs.

v2: Avoid using "H" instead of HALO to keep names uniform - DK.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2016-06-29 10:22:52 -07:00
Michał Winiarski e3623d34ca intel/skl: Add missing SKL PCI IDs
Used by production devices:
    Intel(R) HD Graphics 510
    Intel(R) HD Graphics 535
    Intel(R) Iris(TM) Graphics 550
    Intel(R) Iris(TM) Graphics P555

Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-27 17:45:34 -07:00