Commit Graph

24 Commits (3bede5dbbcd307d9fb675562f780bf9525efb3d4)

Author SHA1 Message Date
Alex Deucher e57be77810 radeon: add new OLAND pci id
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-10 16:26:42 -04:00
Alex Deucher bb0b97e673 radeon: add new bonaire pci id
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-05-26 12:26:40 -04:00
Alex Deucher 22b995d8cb radeon: add new SI pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-21 11:06:33 -04:00
Alex Deucher 3ad801bf1f radeon: add new CIK pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-21 11:04:51 -04:00
Samuel Li 3bdf1f78d8 radeon: add Mullins pci ids
Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-05-02 11:05:31 -04:00
Alex Deucher e8cbc57965 radeon: fix sumo2 pci id
0x9649 is sumo2, not sumo.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-12-24 15:19:34 -05:00
Alex Deucher 1a84eea45b radeon: add hawaii pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-13 11:33:31 -05:00
Alex Deucher 8a2e0fa917 radeon: add berlin pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-06 15:39:37 -04:00
Alex Deucher 378bb47a78 radeon: add kabini pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 14:44:17 -04:00
Alex Deucher 96c04c23fc radeon: add Bonaire pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-28 14:44:10 -04:00
Alex Deucher 96e90aabc4 radeon: add HAINAN pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-13 16:16:14 -04:00
Alex Deucher ec3c257eb6 radeon: add new richland pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-25 14:13:52 -04:00
Alex Deucher 439d7d7432 radeon: add new SI pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-25 14:12:50 -04:00
Alex Deucher 36a2daad24 radeon: add pci ids for Richland APUs
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-03-08 14:12:32 -05:00
Alex Deucher 353f073bc1 radeon: add OLAND pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-04 15:03:55 -05:00
Alex Deucher 171666e4b8 radeon: add new SI pci id
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2012-11-21 18:45:14 -05:00
Alex Deucher a4cb7233a8 radeon: add some new SI pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-10-16 12:58:39 -04:00
Alex Deucher 9f823ca236 radeon: add some new SI pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-06 10:34:59 -04:00
Alex Deucher dd944a0081 radeon: add some missing evergreen pci ids
Noticed by: Harald van Dijk <fdo@gigawatt.nl>

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=53124

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-06 10:33:56 -04:00
Alex Deucher c563db07bf radeon: add new pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-06-05 10:07:15 -04:00
Michel Dänzer 481234f290 radeon: Add Southern Islands PCI IDs.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-05-16 18:49:44 +02:00
Anisse Astier cf7cc62a98 radeon: Add new R600 PCI ids for surface manager
This is the same list of PCI ids added by Alex Deucher in xf86-video-ati commit
aacbd629b02cbee3f9e6a0ee452b4e3f21376bd3.

This is needed since the addition of the surface allocator helper in
commit c51f7f0e46 ; it needs to differentiate
pre and post-R600 GPUs.
Therefore we should maintain another PCI id list.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=48138
Signed-off-by: Anisse Astier <anisse@astier.eu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-05-10 13:07:59 -04:00
Alex Deucher c50cc24690 radeon: add TN surface support
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-03-20 19:33:09 -04:00
Jerome Glisse c51f7f0e46 radeon: add surface allocator helper v10
The surface allocator is able to build complete miptree when allocating
surface for r600/r700/evergreen/northern islands GPU family. It also
compute bo size and alignment for render buffer, depth buffer and
scanout buffer.

v2 fix r6xx/r7xx 2D tiling width align computation
v3 add tile split support and fix 1d texture alignment
v4 rework to more properly support compressed format, split surface pixel
   size and surface element size in separate fields
v5 support texture array (still issue on r6xx)
v6 split surface value computation and mipmap tree building, rework eg
   and newer computation
v7 add a check for tile split and 2d tiled
v8 initialize mode value before testing it in all case, reenable
   2D macro tile mode on r6xx for cubemap and array. Fix cubemap
   to force array size to the number of face.
v9 fix handling of stencil buffer on evergreen
v10 on evergreen depth buffer need to have enough room for a stencil
    buffer just after depth one

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-01 17:11:29 -05:00