dbb0d979cc
nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load.
2007-01-06 17:50:00 +11:00
f80659bc29
Cleanup the nv04 fifo code a bit.
2007-01-05 19:37:06 +01:00
f48a7685bd
For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.
...
When cleaning a fifo, we shouldn't assume everybody use nv40 ;)
Fill DMA_SUBROUTINE fill correct value.
2006-11-28 21:32:03 +01:00
2fd812f8ef
Completely untested NV10/20/30 FIFO context switching changes.
2006-11-14 09:00:31 +11:00
7002082944
Restructure initialisation a bit.
...
- Do important card init in firstopen
- Give each channel it's own cmdbuf dma object
- Move RAMHT config state to the same place as RAMRO/RAMFC
- Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-14 08:11:49 +11:00
2dd3c039fd
fixup fifo size so it is page aligned
2006-11-06 11:42:15 +11:00
b5cf0d635c
Remove hack which delays activation of a additional channel. The previously active channel's state is saved to RAMFC before PFIFO gets clobbered.
2006-10-18 02:37:19 +11:00
55de3f763f
Useful output on a FIFO error interrupt.
2006-10-17 23:44:05 +11:00
1943f39d8c
Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup code a bit.
2006-10-17 06:37:40 +11:00
95486bbde0
Some info on NV40's RAMFC
2006-10-17 06:12:18 +11:00
7ef44b2b8d
Still more work on the context switching code.
2006-10-12 17:31:49 +02:00
dd473411f8
Context switching work.
...
Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet).
Removed the PFIFO_REINIT ioctl. I hope it's that a good idea...
Requires the upcoming commit to the DDX.
2006-10-11 00:28:15 +02:00
fef9b30a2b
initial import of nouveau code from nouveau CVS
2006-08-27 08:55:02 +10:00
Ben Skeggs
Stephane Marchesin
Matthieu Castet
Dave Airlie
Dave Airlie