Commit Graph

72 Commits (88bdb38cea60cea918b6e6a1ca97a7ec3de5b832)

Author SHA1 Message Date
Jesse Barnes 852232fb80 Remove plane->pipe mapping from SAREA private after all
We can figure out which pipe a given plane is mapped to by looking at the
display control registers instead of tracking it in a new SAREA private field.
If this becomes a performance problem, we could move to an ioctl based solution
by adding a new parameter for the DDX to set (defaulting to the old behavior if
the param was never set of course).
2007-09-12 08:55:33 -07:00
Jesse Barnes 3cb8acd5ab Disambiguate planes & pipes for swap operations
This mod makes the SAREA track plane to pipe mappings and corrects the name of
the plane info variables (they were mislabeled as pipe info since until now all
code assumed a direct mapping between planes and pipes).

It also updates the flip ioctl argument to take a set of planes rather than
pipes, since planes are flipped while pipes generate vblank events.
2007-09-11 03:48:46 -07:00
Keith Packard c78e610fa4 Add register defines for hw binning 2007-08-28 12:23:51 -07:00
Dave Airlie da27986870 i915: i965 non-secure batchbuffer bit has moved. 2007-08-11 08:57:53 +10:00
Eric Anholt 5b38e13416 Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.
The data is now in kernel space, copied in/out as appropriate according to the
This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal
with those failures.  This also means that XFree86 4.2.0 support for i810 DRM
is lost.
2007-07-20 18:16:42 -07:00
Eric Anholt c1119b1b09 Replace filp in ioctl arguments with drm_file *file_priv.
As a fallout, replace filp storage with file_priv storage for "unique
identifier of a client" all over the DRM.  There is a 1:1 mapping, so this
should be a noop.  This could be a minor performance improvement, as everything
on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls
went the other direction.
2007-07-20 13:39:45 -07:00
Eric Anholt 05204b9c8d Merge branch 'origin' 2007-07-19 06:31:26 -07:00
Eric Anholt 33a50412c2 Add dry-coded DRM drawable private information storage for FreeBSD.
With this, all modules build again.
2007-07-18 14:22:49 -07:00
Eric Anholt 3f04fe7890 Fix FreeBSD build. 2007-07-16 01:53:06 -07:00
Dave Airlie be85ad0333 drm: detypedef ttm/bo/fence code 2007-07-16 13:37:02 +10:00
Dave Airlie 21ee6fbfb8 drm: remove drmP.h internal typedefs 2007-07-16 12:32:51 +10:00
Dave Airlie 2c9e05cf4c Merge branch 'master' into cleanup
Conflicts:

	libdrm/xf86drm.c
	linux-core/drm_bo.c
	linux-core/drm_fence.c
2007-07-11 11:23:41 +10:00
Michel Dänzer 3d5d41fa98 i915: Fix handling of breadcrumb counter wraparounds. 2007-06-15 17:13:11 +02:00
Thomas Hellstrom b6b5df24b9 Try to make buffer object / fence object ioctl args 64-bit safe.
Introduce tile members for future tiled buffer support.
Allow user-space to explicitly define a fence-class.
Remove the implicit fence-class mechanism.
64-bit wide buffer object flag member.
2007-06-12 12:21:38 +02:00
Wang Zhenyu 109e2a10f2 Add support for the G33, Q33, and Q35 chipsets.
These require that the status page be referenced by a pointer in GTT, rather
than phsyical memory.  So, we have the X Server allocate that memory and tell
us the address, instead.
2007-06-05 11:15:29 -07:00
Dave Airlie 81b811da37 drm/i915: set the bo up at firstopen time not after DMA init
This is required to use TTM to allocate the ring buffer.
2007-03-27 18:01:31 +10:00
Dave Airlie 26aba875e1 more whitespace issues 2007-03-19 08:56:24 +11:00
Michel Dänzer a33859184a i915: Eliminate dev_priv->current_page.
Always use dev_priv->sarea_priv->pf_current_page directly. This allows clients
to modify it as well while they hold the HW lock, e.g. in order to sync pages
between pipes.
2007-02-28 17:48:56 +01:00
Michel Dänzer 1cdc1b6fba i915: Don't emit waits for pending flips before emitting synchronous flips.
The assumption is that synchronous flips are not isolated usually, and waiting
for all of them could result in stalling the pipeline for long periods of time.

Also use i915_emit_mi_flush() instead of an old-fashioned way to achieve the
same effect.
2007-02-28 15:23:19 +01:00
Michel Dänzer 1a0d890a42 i915: Add support for scheduled buffer swaps to be done as flips.
Unfortunately, emitting asynchronous flips during vertical blank results in
tearing. So we have to wait for the previous vertical blank and emit a
synchronous flip.
2007-02-22 17:21:18 +01:00
Michel Dänzer 6f89584e13 i915: Improved page flipping support, including triple buffering.
Pages are tracked independently on each pipe.

Bump the minor version for 3D clients to know page flipping is usable, and
bump driver date.
2007-02-19 15:08:40 +01:00
Michel Dänzer 34aa3393d0 i915: Page flipping enhancements.
Leave it to the client to wait for the flip to complete when necessary,
but wait for a previous flip to complete before emitting another one. This
should help avoid unnecessary stalling of the ring due to pending flips.

Call i915_do_cleanup_pageflip() unconditionally in preclose.
2007-02-19 15:08:40 +01:00
Michel Dänzer 078e430726 i915: Unify breadcrumb emission. 2007-02-19 15:08:40 +01:00
Thomas Hellstrom e0f53e59be Simple fence object sample driver for via, based on idling the GPU.
Buffer object driver for via.
Some changes to buffer object driver callbacks.
Improve fence flushing.
2007-02-16 20:22:24 +01:00
Thomas Hellstrom a78f70faad Merge branch 'ttm-vram-0-1-branch' 2007-02-14 15:33:40 +01:00
Thomas Hellstrom 5c9a7b0f94 Remove an intel-specific hack and replace it with a fence driver callback. 2007-02-14 13:31:35 +01:00
Thomas Hellstrom 53aee3122a I915 accelerated blit copy functional.
Fixed - to System memory copies are implemented by
flipping in a cache-coherent TTM,
blitting to it, and then flipping it out.
2007-02-09 16:36:53 +01:00
Eric Anholt 8918748058 Add chip family flags to i915 driver, and fix a missing '"' in mach64 ID list. 2007-02-07 21:26:01 -08:00
Thomas Hellstrom 609e3b0375 Implement a policy for selecting memory types. 2007-02-06 14:20:33 +01:00
Thomas Hellstrom 3024f23c65 memory manager: Make device driver aware of different memory types.
Memory types are either fixed (on-card or pre-bound AGP) or not fixed
(dynamically bound) to an aperture. They also carry information about:

1) Whether they can be mapped cached.
2) Whether they are at all mappable.
3) Whether they need an ioremap to be accessible from kernel space.

In this way VRAM memory and, for example, pre-bound AGP appear
identical to the memory manager.

This also makes support for unmappable VRAM simple to implement.
2007-01-31 14:50:57 +01:00
Zou Nan hai 7d4e6b1445 vblank interrupt fix 2007-01-24 16:33:21 +08:00
Keith Packard 31daf66962 Revert i915 drm driver name to i915; miniglx doesn't work otherwise
Yes, this driver supports the new memory manager, that is indicated by the
version number being >= 1.7.
2007-01-06 17:40:50 -08:00
Wang Zhenyu 2851c9f5c6 Bump i915 minor for ARB_OC ioctl 2007-01-06 16:26:54 -08:00
Thomas Hellstrom 10150df02b Simplify the AGP backend interface somewhat.
Fix buffer bound caching policy changing, Allow
on-the-fly changing of caching policy on bound buffers if the hardware
supports it.

Allow drivers to use driver-specific AGP memory types for TTM AGP pages.
Will make AGP drivers much easier to migrate.
2006-10-12 12:09:16 +02:00
Thomas Hellstrom 8e908eaf50 Bump driver date. 2006-09-29 14:21:51 +02:00
Michel Dänzer 3620a3ec85 i915: Bump minor again to differentiate from vsync changes. 2006-09-29 12:55:09 +02:00
Michel Dänzer c0bff9f9cd i915: Bump minor for swap scheduling ioctl and secondary vblank support.
(cherry picked from 2627131e5d commit)
2006-09-29 12:55:09 +02:00
Michel Dänzer da75d59cd6 i915: Add ioctl for scheduling buffer swaps at vertical blanks.
This uses the core facility to schedule a driver callback that will be called
ASAP after the given vertical blank interrupt with the HW lock held.
(cherry picked from 257771fa29 commit)
2006-09-29 12:55:08 +02:00
Michel Dänzer 596d7e9984 Add support for secondary vertical blank interrupt to i915 driver.
When the vertical blank interrupt is enabled for both pipes, pipe A is
considered primary and pipe B secondary. When it's only enabled for one pipe,
it's always considered primary for backwards compatibility.
(cherry picked from 0c7d7f4361 commit)
2006-09-29 12:55:08 +02:00
Thomas Hellstrom c52fafa628 Don't enable fence / buffer objects on non-linux systems.
Bump driver minor and date.
2006-09-28 11:33:03 +02:00
Thomas Hellstrom 273eb7833d Add /proc filesystem buffer / fence object accounting.
Check for NULL pointer in the i915 flush handler.
Remove i915_sync_flush declaration.
2006-09-25 11:51:08 +02:00
Thomas Hellstrom f613022cee Allow a "native type" to be associated with a fence sequence.
In the intel case, we can associate a flush with a sequence.
2006-09-15 16:47:09 +02:00
Thomas Hellstrom 99acb79366 Various bugfixes. 2006-09-08 17:24:38 +02:00
Thomas Hellstrom 034fc31292 i915: Only turn on user IRQs when they are needed. 2006-09-05 14:23:18 +02:00
Thomas Hellstrom 44f6d08988 Validation and fencing. 2006-08-31 21:42:29 +02:00
Thomas Hellstrom 7058d06317 Initial i915 buffer object driver 2006-08-22 10:24:48 +02:00
Thomas Hellstrom e089de33e8 i915 fence object driver implementing 2 fence object types:
0x00 EXE fence. Signals when command stream interpreter has reached the point
where the fence was emitted.
0x01 FLUSH fence. Signals when command stream interpreter has reached the point
where the fence was emitted, and all previous drawing operations have been
completed and flushed.
Implements busy wait (for fastest response time / high CPU) and
lazy wait (User interrupt or timer driven).
2006-08-21 21:36:00 +02:00
Dave Airlie 7a46d41399 i965 code and Linux coding style < 0
smack my whitespace up.
2006-08-10 14:38:50 +10:00
Alan Hourihane 48cb9aceed Add support for Intel i965G chipsets.
This is a patch prepared by Guangdeng Liao based off of Tungsten Graphics's
final code drop.
2006-08-08 15:05:54 -07:00
Keith Packard f8891ef802 i915: Save vblank pipe configuration to restore on resume 2006-06-21 00:15:10 +00:00