Commit Graph

4173 Commits (d275f99c9a7d915473034e6abd575f35bea5db9c)

Author SHA1 Message Date
Keith Packard 1c2dd98267 [intel] Switch to using IMR instead of IER 2008-06-23 10:07:47 -07:00
Keith Packard 61caf797ae [intel-gem] pwrite through GTT
Pin/copy_from_user/unpin through the GTT to eliminate clflush costs.
Benchmarks say this helps quite a bit.
2008-06-23 00:53:53 -07:00
Keith Packard a0ebcbe9d4 [intel] allow the irq code to use either enable or mask registers
still not sure which works best on which hardware; this will make it easier
to experiment.
2008-06-23 00:53:04 -07:00
Maarten Maathuis 30f153a7c2 nouveau: disable KMS for pre-NV50 even when specifically enabled 2008-06-22 19:31:55 +02:00
Maarten Maathuis b0b0f37443 NV50: Fix a few more possible leaks. 2008-06-22 19:04:22 +02:00
Maarten Maathuis 7c9551a464 fix typo 2008-06-22 18:58:04 +02:00
Maarten Maathuis e67cd7dda9 NV50: A few minor added safeties + cleanup. 2008-06-22 18:47:51 +02:00
Ben Skeggs 01e8f0ea42 nv50: oops, keep VRAM allocations aligned at 64KiB - that's our page size.. 2008-06-23 02:42:15 +10:00
Ben Skeggs 89cf2ee2e5 nv50: use same dma object for fb/tt access
We depend on the VM fully now for memory protection, separate DMA objects
for VRAM and GART are unneccesary.  However, until the next interface break
(soon) a client can't depend on the objects being the same and must still
call NV_OBJ_SET_DMA_* methods appropriately.
2008-06-23 01:24:11 +10:00
Maarten Maathuis 3809209349 Undo something i didn't want to change.
- I made it consistent with recent kernel fb code (maybe this is older bugged code?)
- Still i don't use this and i should leave it to others.
2008-06-22 17:01:30 +02:00
Ben Skeggs b9ed0f9950 nouveau: allocate drm-use vram buffers from end of vram.
This avoids seeing garbage from engine setup etc before X gets around
to pointing the CRTCs at a new scanout buffer.  Not actually a noticable
problem before G80 as PRAMIN is forced to the end of VRAM by the hardware
already.
2008-06-23 01:00:42 +10:00
Maarten Maathuis 473a1997ac NV50: Initial import of kernel modesetting. 2008-06-22 16:29:00 +02:00
Dave Airlie 11f2a2ed6f agp: use true/false instead of TRUE/FALSE 2008-06-22 18:25:22 +10:00
Alex Deucher 207f701e1a RADEON: 0x1002 0x5657 is actually an RV410
See bug 14289
2008-06-21 10:46:55 -04:00
Keith Packard a369bf0e57 [intel] Use IMR instead of IER to pend interrupts during ISR
Noting that the interrupt mask register was more reliable than the interrupt
enable register for managing interrupts in user_irq_on/user_irq_off, this
patch replaces the remaining IER frobbing with IMR instead.

The test which exposes IER related failures is:

$ glxgears & glxgears & glxgears
(reposition the glxgears windows away from the upper left corner)
$ while :; do x11perf -rect100 -reps 800 -repeat 1; sleep 1; done &
$ while :; do runoa; runet; done &
2008-06-21 00:33:07 -07:00
Keith Packard 8be6ec491f [intel-gem] Add /proc/dri/*/i915_gem_interrupt
This tracks most of the interrupt-related status, including the
interrupt registers in the chip and the sequence number variables.
2008-06-21 00:13:18 -07:00
Keith Packard 33114e4a11 [intel] Count received interrupts
Another patch adds this to a /proc/dri file for debugging and monitoring.
2008-06-21 00:12:21 -07:00
Keith Packard f4bd566e0b [intel-gem] Remove unused variable. 2008-06-21 00:10:10 -07:00
Keith Packard 54817317e9 [intel-gem] Use polling in i915_gem_idle instead of interrupts.
While waiting for the hardware to idle on leavevt or lastclose, poll
for the sync sequence number instead of waiting for an interrupt. This
allows the code to bail if the hardware hangs for some reason. Also, this
avoids issues with signals as the exisiting wait function is interruptible.
2008-06-20 21:10:42 -07:00
Keith Packard 71b1623e22 [intel-gem] Add intel-specific /proc entries to help monitor gem operation
This adds gem_active, gem_flushing, gem_inactive, gem_request and gem_seqno
entries to monitor gem operation and help debug issues.
2008-06-20 21:07:46 -07:00
Keith Packard 2bd9799e4c Add device-specific proc_init and proc_cleanup hooks
This allows device drivers to add proc files
2008-06-20 16:40:14 -07:00
Keith Packard 918420deef [intel-gem] Use shmem_getpage instead of find_or_create_page
find_or_create_page doesn't quite set up pages correctly; any newly created
pages aren't hooked into the shmem object quite right; user space mmaps of
those pages end up mapping pages full of zeros which then get written to the
real pages inappropriately. This patch requires that the kernel export
shmem_getpage.
2008-06-20 00:21:57 -07:00
Keith Packard 52e5d24fae [intel-gem] Add DRM_IOCTL_I915_GEM_SW_FINISH to flag CPU writes
When a software fallback has completed, usermode must notify the kernel so
that any scanout buffers can be synchronized. This ioctl should be called
whenever a fallback completes to flush CPU and chipset caches.
2008-06-20 00:21:57 -07:00
Dave Airlie 1915de2c56 drm: only use kernel ioctl cmd when doing a core ioctl.
Need to overhaul the mess that is driver ioctls
2008-06-20 15:35:47 +10:00
Dave Airlie 9d79944a93 r300: fix warning 2008-06-20 15:35:16 +10:00
Dave Airlie 8712f0a17b drm: fix the ioctl to not believe userspace.
believing userspace causes oopses
2008-06-20 12:03:41 +10:00
Jesse Barnes f58e21c7d0 i915: add blanking support to intelfb
Got tired of not having my LCD actually turn off when I left the machine at the
console.
2008-06-18 16:49:51 -07:00
Jesse Barnes 57b8837b4e i915: cleanup PCI state before disabling MSI
Core MSI code will BUG() if an interrupt handler is still registered when
pci_disable_msi() is called.
2008-06-18 15:31:48 -07:00
Jesse Barnes 86accbcb34 Merge commit 'origin/drm-gem' into modesetting-gem
Lots of conflicts, seems to load ok, but I'm sure some bugs snuck in.

Conflicts:

	linux-core/drmP.h
	linux-core/drm_lock.c
	linux-core/i915_gem.c
	shared-core/drm.h
	shared-core/i915_dma.c
	shared-core/i915_drv.h
	shared-core/i915_irq.c
2008-06-18 15:25:54 -07:00
Jesse Barnes c843d47b90 i915: use WC mapping for framebuffer screen_base 2008-06-18 14:51:46 -07:00
Jesse Barnes 241ff808b0 Merge branch 'modesetting-101' into modesetting-gem 2008-06-18 14:01:47 -07:00
Jesse Barnes 7010d50007 i915: switch back to fbcon on panic
Normally when X is running, panic messages will be invisible and the machine
will just appear to hard hang.  This patch adds support for switching back to
the fbcon framebuffer on panic (through the use of a panic notifier
registration) so we can see what happened.

Note that in order to be really useful, X will have to run its VT in something
other than KD_GRAPHICS mode.  Also, not all kernel errors result in panics,
some go through BUG() which may trigger another type of event, not resulting in
a switch.
2008-06-18 13:57:39 -07:00
Zhenyu Wang 00f549bd5f i915: Add support for Intel 4 series chipsets
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
2008-06-18 14:19:38 +08:00
Eric Anholt e7424e4580 [intel] Quirk away MSI support on 945G/GM.
The PCI caps register reports MSI support even though it isn't really there.
2008-06-16 15:15:02 -07:00
Eric Anholt c847271179 [linux] Use the device's irq for handler setup instead of stale dev->irq.
This fixes registration when MSI is set up after the stub function fills in
dev->irq.  Otherwise /proc/interrupts would report attachment to the fasteoi
interrupt.  dev->irq is still exposed (and updated at IRQ setup)
for the drivers that use it for whatever reason.
2008-06-16 15:09:11 -07:00
Jerome Glisse 59112c9e52 radeon: *really* fix screen corruption thanks to Lukasz Krotowski 2008-06-15 20:18:29 +02:00
Jerome Glisse 6f8cc95703 radeon: actualy try to fix the corruption 2008-06-15 19:31:02 +02:00
Jerome Glisse 9dd58d6568 radeon: fix screen corruption introduced by last patch 2008-06-15 18:49:47 +02:00
Keith Packard 3e48e14499 [intel-gem] Execute MI_FLUSH in leavevt_ioctl
In leavevt_ioctl, queue an MI_FLUSH and then block waiting for it to
complete. This will empty the active and flushing lists. That leaves only
the inactive list to evict.
2008-06-13 19:49:47 -07:00
Keith Packard 19c3418848 [intel-gem] inactive list may contain objects in CPU write domain
Pin/unpin need to know whether to remove/add objects from the inactive list,
inactive objects cannot be in any GPU write domain as those would be on the
flushing list instead. However, inactive objects may be in the CPU write
domain.
2008-06-13 19:47:23 -07:00
Keith Packard 93c2871ecc [intel-gem] BUG_ON active objects in gem_object_unbind
Now that gem_object_unbind waits for rendering to complete, objects should
not be active when they are being pulled from the GTT. BUG_ON if this is
broken.
2008-06-13 19:43:40 -07:00
Keith Packard 68856b619b [intel-gem] Debugging -- verify inactive list invariants
Inactive list elements may not be pinned, active or have non-CPU write
domains.
2008-06-13 19:40:16 -07:00
Keith Packard 732b196074 [intel-gem] whitespace fixes 2008-06-13 19:37:44 -07:00
Keith Packard a7139cb851 [intel-gem] show total GTT space in /proc/dri/*/gem_objects 2008-06-13 19:35:22 -07:00
Keith Packard 73bc18cad8 [intel-gem] Wait for rendering to complete before unbinding.
Moving to the CPU domain doesn't ensure that rendering is finished, the
buffer may still be in use as a texture or other data source.
2008-06-13 17:06:35 -07:00
Keith Packard 8b9ab108ec [libdrm] Restart all ioctls on signal receipt
Receiving a signal should be ignored by the library, so just restart any
ioctl which returns EINTR or EAGAIN.
2008-06-13 16:03:22 -07:00
Keith Packard 217beb9c8d [intel-gem] add gtt and pin counts to /proc/dri/*/gem_objects
Not quite portable, but these are useful for intel. Some more general
mechanism could be done...
2008-06-13 15:43:02 -07:00
Keith Packard 4086cdb655 [intel-gem] Left the last exec buffer pinned. oops.
Loop end variable 'pinned' was set one too low.
2008-06-13 15:38:13 -07:00
Robert Noland 29ffa0017d [FreeBSD] Fix another lock leak
Reported by vehemens
2008-06-13 17:41:34 -04:00
Keith Packard baf5213694 [intel-gem] Pin objects during execbuffer
Pinning the objects avoids accidentally evicting them while binding
other objects.
2008-06-13 14:29:46 -07:00