Commit Graph

1479 Commits (e7424e4580159b0ac3e232674dff5c862e851dff)

Author SHA1 Message Date
Eric Anholt e7424e4580 [intel] Quirk away MSI support on 945G/GM.
The PCI caps register reports MSI support even though it isn't really there.
2008-06-16 15:15:02 -07:00
Eric Anholt c847271179 [linux] Use the device's irq for handler setup instead of stale dev->irq.
This fixes registration when MSI is set up after the stub function fills in
dev->irq.  Otherwise /proc/interrupts would report attachment to the fasteoi
interrupt.  dev->irq is still exposed (and updated at IRQ setup)
for the drivers that use it for whatever reason.
2008-06-16 15:09:11 -07:00
Keith Packard 3e48e14499 [intel-gem] Execute MI_FLUSH in leavevt_ioctl
In leavevt_ioctl, queue an MI_FLUSH and then block waiting for it to
complete. This will empty the active and flushing lists. That leaves only
the inactive list to evict.
2008-06-13 19:49:47 -07:00
Keith Packard 19c3418848 [intel-gem] inactive list may contain objects in CPU write domain
Pin/unpin need to know whether to remove/add objects from the inactive list,
inactive objects cannot be in any GPU write domain as those would be on the
flushing list instead. However, inactive objects may be in the CPU write
domain.
2008-06-13 19:47:23 -07:00
Keith Packard 93c2871ecc [intel-gem] BUG_ON active objects in gem_object_unbind
Now that gem_object_unbind waits for rendering to complete, objects should
not be active when they are being pulled from the GTT. BUG_ON if this is
broken.
2008-06-13 19:43:40 -07:00
Keith Packard 68856b619b [intel-gem] Debugging -- verify inactive list invariants
Inactive list elements may not be pinned, active or have non-CPU write
domains.
2008-06-13 19:40:16 -07:00
Keith Packard 732b196074 [intel-gem] whitespace fixes 2008-06-13 19:37:44 -07:00
Keith Packard a7139cb851 [intel-gem] show total GTT space in /proc/dri/*/gem_objects 2008-06-13 19:35:22 -07:00
Keith Packard 73bc18cad8 [intel-gem] Wait for rendering to complete before unbinding.
Moving to the CPU domain doesn't ensure that rendering is finished, the
buffer may still be in use as a texture or other data source.
2008-06-13 17:06:35 -07:00
Keith Packard 217beb9c8d [intel-gem] add gtt and pin counts to /proc/dri/*/gem_objects
Not quite portable, but these are useful for intel. Some more general
mechanism could be done...
2008-06-13 15:43:02 -07:00
Keith Packard 4086cdb655 [intel-gem] Left the last exec buffer pinned. oops.
Loop end variable 'pinned' was set one too low.
2008-06-13 15:38:13 -07:00
Keith Packard baf5213694 [intel-gem] Pin objects during execbuffer
Pinning the objects avoids accidentally evicting them while binding
other objects.
2008-06-13 14:29:46 -07:00
Keith Packard ced9ebf645 [intel-gem] throttle based on frames rather than time. Reduces jitter.
Record the last execbuffer sequence for each client.
Record that sequence in the throttle ioctl as the 'throttle sequence'.
Wait for the last throttle sequence in the throttle ioctl.
2008-06-13 14:29:46 -07:00
Keith Packard 6b2cba1ecc [intel-gem] evict_something was failing when wait_request freed objects
When i915_wait_request clears object from the active list, it may end up
freeing them and not moving them to the inactive list. This ends up
unbinding objects from the GTT without there ever being new objects visible
to i915_gem_evict_something on the inactive list. As the only success
condition required the presence of objects on the inactive list, this would
falsely assume that no GTT space had been made available, and end up
returning -ENOMEM to the application.
2008-06-13 14:29:46 -07:00
Keith Packard 3762c9ea67 [intel] Enable MSI for i915 IRQ 2008-06-13 14:29:46 -07:00
Keith Packard 462af73149 [intel-gem] Use a delayed_work instead of a timer + work_struct
We want request retirement to occur about once a second when the request
queue is non-empty. This was done with a timer that queued a work_struct,
using a delayed_work instead makes a lot more sense.
2008-06-13 14:29:46 -07:00
Keith Packard e5364914ac [intel-gem] Reorder i915_add_request to schedule work last
i915_add_request was calling schedule_delayed_work before adding the request
to the list; it makes more sense to do that last.
2008-06-13 14:29:45 -07:00
Keith Packard f378319b56 Use /bin/pwd instead of trusting shell built-in 2008-06-13 14:29:45 -07:00
Eric Anholt c892e26bdf [gem] Don't require the lock in execbuf now that it's not needed for the ring. 2008-06-13 09:49:05 -07:00
Eric Anholt b2606e325a [gem] Remove the drm_client_lock_take in set_domain.
We no longer need to use it to protect against shared ringbuffer access.
2008-06-11 16:19:23 -07:00
Eric Anholt 846d792ac1 [gem] Another round of cleanups from checkpatch.pl 2008-06-11 15:51:17 -07:00
Eric Anholt 2655005762 [gem] Move potentially device-specific ioctls to the intel driver.
This is the create (may want location flags), pread/pwrite/mmap
(performance tuning hints), and set_domain (will 32 bits be enough for
everyone?) ioctls.  Left in the generic set are just flink/open/close.

The 2D driver must be updated for this change, and API but not ABI is broken
for 3D.  The driver version is bumped to mark this.
2008-06-11 14:42:40 -07:00
Eric Anholt 2a35d857b3 Remove override of drm module list in preparation for merge. 2008-06-11 12:20:56 -07:00
Eric Anholt dac3bcb414 [gem] Remove carefully-sprinkled i915_kernel_lost_context().
They are not unnecessary since the kernel's the only thing touching the ring.
2008-06-11 11:28:20 -07:00
Eric Anholt 2150da5d1a [gem] Manage the ringbuffer from the kernel in the GEM case.
This requires that the X Server use the execbuf interface for buffer
submission, as it no longer has direct access to the ring.  This is
therefore a flag day for the gem interface.

This also adds enter/leavevt ioctls for use by the X Server.  These would
get stubbed out in a modesetting implementation, but are required while
in an environment where the device's state is only managed by the DRM while
X has the VT.
2008-06-10 22:57:07 -07:00
Keith Packard 6cd0ef06a6 [intel] remove settable use_mi_batchbuffer_start
The driver can know what hardware requires MI_BATCH_BUFFER vs
MI_BATCH_BUFFER_START; there's no reason to let user mode configure this.
2008-06-06 13:26:03 -07:00
Keith Packard 9f46c6935d [intel-gem] Use timers to retire requests periodically.
Without the user IRQ running constantly, there's no wakeup when the ring
empties to go retire requests and free buffers. Use a 1 second timer to make
that happen more often.
2008-06-06 13:00:47 -07:00
Keith Packard 56a96841d0 [intel-gem] Add explicit throttle ioctl
Instead of throttling and execbuffer time, have the application ask to
throttle explicitly. This allows the throttle to happen less often, and
without holding the DRM lock.
2008-06-06 13:00:46 -07:00
Keith Packard 118baeee18 [intel-gem] Dump error status on wait_request failure 2008-06-06 13:00:46 -07:00
Keith Packard 0903de0c8f Drop struct_mutex while waiting in drm_client_lock_take
struct_mutex cannot be held while blocking on DRM lock.
2008-06-03 21:49:57 -07:00
Keith Packard 867c2bb461 [intel-gem] reloc_and_validate_object → object_bind_and_relocate
Just renaming this function and related parameters to match terminology used
elsewhere in the driver.
2008-06-02 12:37:10 -07:00
Keith Packard 1cb2940a25 [intel-gem] Propagate set_domain errors.
set_domain can block waiting for rendering to complete. If that process is
interrupted by a signal, it can return -EINTR. Catch this error in all
callers and correctly deal with the result.
2008-06-02 10:59:15 -07:00
Eric Anholt 461bfa3da6 Merge commit 'origin/master' into drm-gem
Conflicts:

	linux-core/Makefile.kernel
	shared-core/i915_drv.h
	shared-core/nouveau_state.c
2008-05-30 14:42:08 -07:00
Eric Anholt 50bce2bc62 [intel-gem] Only update obj->write_domain if we're actually changing it.
The problem was revealed where on 965, the display list vertex buffer would see:

create		      -> (CPU, CPU)
set_domain (CPU, CPU) -> (CPU, CPU)
set_comain (CPU, 0)   -> (CPU, 0) (no clflush occurred)
execbuf	   (GPU, 0)   -> (CPU+GPU, 0) (still no clflush)

instead of:

create		      -> (CPU, CPU)
set_domain (CPU, CPU) -> (CPU, CPU)
set_comain (CPU, 0)   -> (CPU, CPU)
execbuf	   (GPU, 0)   -> (CPU+GPU, 0) (clflushed)
2008-05-30 13:47:34 -07:00
Eric Anholt 4f92ed3427 [intel-gem] Add an option to check GTT versus CPU coherency at execbuf time. 2008-05-30 12:42:48 -07:00
Eric Anholt 3b1e4e6dc3 [intel-gem] Write the presumed_offset back out after updating it.
Otherwise, 965 constant state buffers get re-relocated every exec.  Ouch.
2008-05-29 12:53:21 -07:00
Keith Packard 19ff3366e4 [intel-gem] Clean up active/inactive/flushing list debugging. 2008-05-28 23:56:31 -07:00
Dave Airlie 5b86823fa3 radeon: split microcode out into a separate header file. 2008-05-28 11:12:57 +10:00
Eric Anholt e10502002f [intel-gem] Replace idlelock usage with real lock acquisition. 2008-05-27 18:03:18 -07:00
Keith Packard 1f4e36081b [intel-gem] Must hold DRM lock while setting object domain
Object domain transfer can involve adding flush ops to the request queue,
and so the DRM lock must be held to avoid having the X server smash pointers
badly.
2008-05-26 17:41:46 -07:00
Keith Packard d434b64f6a [i915] leave interrupts masked off when not in use.
The interrupt enable register cannot be used to temporarily disable
interrupts, instead use the interrupt mask register.

Note that this change means that a pile of buffers will be left stuck on the
chip as the final interrupts will not be recognized to come and drain things.
2008-05-26 03:25:16 -07:00
Keith Packard 7cf3fd29fe [intel-gem] Add DRM_I915_GEM_BUSY ioctl to check for idle buffers.
This new ioctl returns whether re-using the buffer would force a wait.
2008-05-25 20:45:20 -07:00
Keith Packard 6d1d11704a [intel-gem] Compute npages instead of nbytes in flush_pwrite
i915_gem_flush_pwrite optimizes short writes to the buffer by clflushing
only the modified pages, but it was miscomputing the number of pages.
2008-05-25 20:44:19 -07:00
Keith Packard c69b81df62 [intel-gem] replace call to jiffies_to-msec with simple inline 2008-05-25 20:41:42 -07:00
Keith Packard 8c2b207f9b [intel-gem] Encourage multiple caches to hold read data
When reading from multiple domains, allow each cache to continue
to hold data until writes occur somewhere. This is done by
first leaving the read_domains alone at bind time (presumably the CPU read
cache contains valid data still) and then in set_domain, if no write_domain
is specified, the new read domains are simply merged into the existing read
domains.

A huge comment was added above set_domain to explain how things are
expected to work.
2008-05-22 23:08:38 -07:00
Keith Packard 44ed693ca6 [gem] Use CPU domain for new or pageable objects
Newly allocated objects need to be in the CPU domain as they've just been
cleared by the CPU. Also, unmapping objects from the GTT needs to put them
into the CPU domain, both to flush rendering as well as to ensure that any
paging action gets flushed before we remap to the GTT.
2008-05-22 22:00:21 -07:00
Keith Packard 71b09a5f75 [intel-gem] Force ring retire by emiting flush before user-interrupt.
Commands in the ring are parsed and started when the head pointer passes by
them, but they are not necessarily finished until a MI_FLUSH happens. This
patch inserts a flush after the execbuffer (the only place a flush wasn't
already happening).
2008-05-22 22:00:21 -07:00
Keith Packard da3f099a7c [intel-gem] invalidate ring locals for pin/unpin/set_domain/free functions
Ring locals must be reloaded from hardware in case the X server ran.
2008-05-22 22:00:21 -07:00
Eric Anholt 5e662f90d1 [gem] Release GEM buffers from work task scheduled from IRQ.
There are now 3 lists.  Active is buffers currently in the ringbuffer.
Flushing is not in the ringbuffer, but needs a flush before unbinding.
Inactive is as before.  This prevents object_free → unbind →
wait_rendering → object_reference and a kernel oops about weird refcounting.

This also avoids an synchronous extra flush and wait when freeing a buffer
which had a write_domain set (such as a temporary rendered to and then from
using the 2d engine).  It will sit around on the flushing list until the
appropriate flush gets emitted, or we need the GTT space for another
operation.
2008-05-22 22:00:21 -07:00
Eric Anholt d6f7968577 [gem] Replace ring throttling hack with actual time measurement. 2008-05-21 16:40:14 -07:00