Add the new DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* defines from v4.14-rc1
kernel.
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
Signed-off-by: Rob Herring <robh@kernel.org>
As part of Treble project in Android O, all the device specific files have
to be located in a separate vendor partition. This is done by setting
LOCAL_PROPRIETARY_MODULE (the name is misleading). This change will not
break existing platforms without a vendor partition as it will just move
files to /system/vendor.
Signed-off-by: Rob Herring <robh@kernel.org>
In uvd encode parameter package, parameters input_pic_luma_pitch and
input_pic_chroma_pitch should be picture width align with hardware alignment.
The hardware alignment is 16 for amdgpu family earlier than AMDGPU_FAMILY_AI,
and 256 for later than and including AMDGPU_FAMILY_AI.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Query hardware IP information to find out if there are uvd encode rings
ready for use in kernel driver.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Adding initial tests for locks detection when SW
scheduler FIFO is full.
The test works by submitting a batch of identical commands which make the CP
stall waiting for condition to become true. The condition is later satisfied
form a helper thread. Other events that happen during this time
might create deadlock situations. One such example is GPU reset
triggered by this stall when amdgpu_lockup_timeout != 0.
v2:
Increase the delay from 2 to 100 ms.
Comment out the compute test until it's working.
Typos fix.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Fixes this warning:
freedreno/kgsl/kgsl_ringbuffer.c: In function ‘kgsl_ringbuffer_flush’:
freedreno/kgsl/kgsl_ringbuffer.c:149:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
req.timestamp = (uint32_t)kgsl_ring->bo->hostptr;
^
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
If drmPrimeFDToHandle fails in etna_bo_from_dmabuf, the function must
not return with the table_lock mutex held. Unlock the mutex in the error
path.
Based on ceb70a6b10 ("freedreno: prevent deadlock in error path").
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Fixes crash when/usr/share/libdrm/amdgpu.ids contains ASIC_ID_TABLE_NUM_ENTRIES + 1 entries.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102432
Fixes: 7e6bf88cac (amdgpu: move asic id table to a separate file)
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Fixes the tarball generation.
fixes: 9d133dd087 (tests/amdgpu: add uvd encode unit tests)
bug: https://bugs.freedesktop.org/show_bug.cgi?id=102391
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Look up BOs from the name table using the name parameter instead of
req.handle (which at this point is always zero).
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Define two macros to avoid building errors.
Fixes: 7e6bf88cac (amdgpu: move asic id table to a separate file)
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
since bo_reference and bo_internal_free are
all only used by bo_free, so we just merge them
together
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
there is race issue between two threads on amdgpu_bo_reference and
amdgpu_bo_import, this patch tends to fix it by moving the
pthread_mutex_lock out of bo_free_internal and move to bo_reference
to cover the update_reference part.
The mutex_unlock in bo_import should also cover bo refcount
increasement.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
`ring` cannot be non-null, so the label reduces to a simple return.
Then, there is no point initialising `ring` just to overwrite it before
anyone reads it.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
`pipe` cannot be non-null, so the label reduces to a simple return.
Then, there is no point initialising `pipe` just to overwrite it before
anyone reads it.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
GCC 7 started warning when a switch case has neither a `break` nor
a "fallthrough" comment.
Let's be explicit that we meant to fall through here.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Analogous to previous commit (and the rest of the codebase), simply
discard the device if we cannot parse it.
Fixes: f8484ccbd1 ("xf86drm: Add USB support")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
On ChromeOS devices, readdir() processes the directory in
the following order:
-NAME- -TYPE-
. n/a
.. n/a
vgem n/a
card1 DRM_BUS_PLATFORM
renderD129 DRM_BUS_PLATFORM
card0 DRM_BUS_PCI
renderD128 DRM_BUS_PCI
controlD64 DRM_BUS_PCI
In drmGetDevices2, after drmProcessPlatformDevice fails for
/dev/dri/card1, we don't process the remaining directory entries.
As such, Vulkan fails to initialize since Mesa uses drmGetDevices2.
To fix this, continue if drmProcessPlatformDevice fails.
Fixes: 7b1f37f474 ("xf86drm: Add platform and host1x bus support")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil: correct the host1x platforms as well]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
This just sends chunks to the kernel API for a single command
stream.
This should provide a more future proof and extensible API
for command submission.
v2: use amdgpu_bo_list_handle, add two helper functions to
access bo and context internals.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
These are just wrappers using the amdgpu device handle.
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
It is safe to submit the full struct even on older kernels as such
kernels do not process the full struct. Without this change it
becomes quite challenging to extned the submit struct.
Freedreno has no special treatment too. See git commits
- freedreno: sync uapi header
- freedreno: add fence fd support
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
No functional change. Just organizing the code
so it gets clear for future platforms.
Paulo deserves credits becuase he was the one
that just noticed this IS_9XX was in the wrong position
after CNL patches got introduced.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
As far as I understand, IS_9XX should return true for it.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
By the Spec all CNL Y skus are 2+2, i.e. GT2.
This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
v2: Add kernel commit id for reference.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is a copy of merged i915's
commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")
v2: Remove PCI IDs for SKU not mentioned in spec.
v3: Add kernel commit id for reference.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Add the PCI IDs for U SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Add the PCI IDs for H SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Add the PCI IDs for S SKU IN CFL by following the spec.
v2: Update IDs.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Marek Olšák
Dave Airlie
Rob Herring
James Zhu
Andrey Grodzovsky
Christian König
Anuj Phogat
Eric Engestrom
Philipp Zabel
Jan Vesely
Alex Deucher
Daniel Stone
Chih-Wei Huang
Boyuan Zhang
Jason Ekstrand
Monk Liu
Eric Engestrom
Flora Cui
Hawking Zhang
Emil Velikov
Gurchetan Singh
Lucas Stach
coypu
Christian Gmeiner
Rodrigo Vivi
Paulo Zanoni
Ben Widawsky
Anusha Srivatsa