319 lines
8.0 KiB
C
319 lines
8.0 KiB
C
#include "drmP.h"
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#include "nouveau_drv.h"
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#define NV_CTXDMA_PAGE_SHIFT 12
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#define NV_CTXDMA_PAGE_SIZE (1 << NV_CTXDMA_PAGE_SHIFT)
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#define NV_CTXDMA_PAGE_MASK (NV_CTXDMA_PAGE_SIZE - 1)
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struct nouveau_sgdma_be {
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struct drm_ttm_backend backend;
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struct drm_device *dev;
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int pages;
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int pages_populated;
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dma_addr_t *pagelist;
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int is_bound;
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unsigned int pte_start;
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};
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static int
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nouveau_sgdma_needs_ub_cache_adjust(struct drm_ttm_backend *be)
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{
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return ((be->flags & DRM_BE_FLAG_BOUND_CACHED) ? 0 : 1);
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}
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static int
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nouveau_sgdma_populate(struct drm_ttm_backend *be, unsigned long num_pages,
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struct page **pages)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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int p, d, o;
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DRM_DEBUG("num_pages = %ld\n", num_pages);
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if (nvbe->pagelist)
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return -EINVAL;
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nvbe->pages = (num_pages << PAGE_SHIFT) >> NV_CTXDMA_PAGE_SHIFT;
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nvbe->pagelist = drm_alloc(nvbe->pages*sizeof(dma_addr_t),
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DRM_MEM_PAGES);
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nvbe->pages_populated = d = 0;
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for (p = 0; p < num_pages; p++) {
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for (o = 0; o < PAGE_SIZE; o += NV_CTXDMA_PAGE_SIZE) {
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nvbe->pagelist[d] = pci_map_page(nvbe->dev->pdev,
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pages[p], o,
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NV_CTXDMA_PAGE_SIZE,
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PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(nvbe->pagelist[d])) {
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be->func->clear(be);
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DRM_ERROR("pci_map_page failed\n");
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return -EINVAL;
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}
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nvbe->pages_populated = ++d;
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}
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}
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return 0;
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}
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static void
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nouveau_sgdma_clear(struct drm_ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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int d;
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DRM_DEBUG("\n");
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if (nvbe && nvbe->pagelist) {
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if (nvbe->is_bound)
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be->func->unbind(be);
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for (d = 0; d < nvbe->pages_populated; d--) {
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pci_unmap_page(nvbe->dev->pdev, nvbe->pagelist[d],
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NV_CTXDMA_PAGE_SIZE,
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PCI_DMA_BIDIRECTIONAL);
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}
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drm_free(nvbe->pagelist, nvbe->pages*sizeof(dma_addr_t),
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DRM_MEM_PAGES);
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}
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}
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static int
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nouveau_sgdma_bind(struct drm_ttm_backend *be, unsigned long pg_start,
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int cached)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
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struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
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uint64_t offset = (pg_start << PAGE_SHIFT);
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uint32_t i;
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DRM_DEBUG("pg=0x%lx (0x%llx), cached=%d\n", pg_start, offset, cached);
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if (offset & NV_CTXDMA_PAGE_MASK)
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return -EINVAL;
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nvbe->pte_start = (offset >> NV_CTXDMA_PAGE_SHIFT);
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if (dev_priv->card_type < NV_50)
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nvbe->pte_start += 2; /* skip ctxdma header */
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for (i = nvbe->pte_start; i < nvbe->pte_start + nvbe->pages; i++) {
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uint64_t pteval = nvbe->pagelist[i - nvbe->pte_start];
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if (pteval & NV_CTXDMA_PAGE_MASK) {
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DRM_ERROR("Bad pteval 0x%llx\n", pteval);
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return -EINVAL;
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}
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if (dev_priv->card_type < NV_50) {
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INSTANCE_WR(gpuobj, i, pteval | 3);
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} else {
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INSTANCE_WR(gpuobj, (i<<1)+0, pteval | 0x21);
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INSTANCE_WR(gpuobj, (i<<1)+1, 0x00000000);
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}
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}
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nvbe->is_bound = 1;
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return 0;
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}
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static int
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nouveau_sgdma_unbind(struct drm_ttm_backend *be)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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struct drm_nouveau_private *dev_priv = nvbe->dev->dev_private;
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DRM_DEBUG("\n");
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if (nvbe->is_bound) {
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struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
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unsigned int pte;
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pte = nvbe->pte_start;
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while (pte < (nvbe->pte_start + nvbe->pages)) {
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uint64_t pteval = dev_priv->gart_info.sg_dummy_bus;
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if (dev_priv->card_type < NV_50) {
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INSTANCE_WR(gpuobj, pte, pteval | 3);
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} else {
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INSTANCE_WR(gpuobj, (pte<<1)+0, 0x00000010);
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INSTANCE_WR(gpuobj, (pte<<1)+1, 0x00000004);
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}
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pte++;
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}
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nvbe->is_bound = 0;
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}
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return 0;
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}
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static void
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nouveau_sgdma_destroy(struct drm_ttm_backend *be)
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{
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DRM_DEBUG("\n");
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if (be) {
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be;
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if (nvbe) {
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if (nvbe->pagelist)
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be->func->clear(be);
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drm_ctl_free(nvbe, sizeof(*nvbe), DRM_MEM_TTM);
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}
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}
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}
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static struct drm_ttm_backend_func nouveau_sgdma_backend = {
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.needs_ub_cache_adjust = nouveau_sgdma_needs_ub_cache_adjust,
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.populate = nouveau_sgdma_populate,
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.clear = nouveau_sgdma_clear,
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.bind = nouveau_sgdma_bind,
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.unbind = nouveau_sgdma_unbind,
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.destroy = nouveau_sgdma_destroy
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};
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struct drm_ttm_backend *
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nouveau_sgdma_init_ttm(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_sgdma_be *nvbe;
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if (!dev_priv->gart_info.sg_ctxdma)
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return NULL;
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nvbe = drm_ctl_calloc(1, sizeof(*nvbe), DRM_MEM_TTM);
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if (!nvbe)
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return NULL;
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nvbe->dev = dev;
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nvbe->backend.func = &nouveau_sgdma_backend;
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nvbe->backend.mem_type = DRM_BO_MEM_TT;
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return &nvbe->backend;
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}
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int
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nouveau_sgdma_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = NULL;
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uint32_t aper_size, obj_size;
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int i, ret;
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if (dev_priv->card_type < NV_50) {
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aper_size = (64 * 1024 * 1024);
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obj_size = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 4;
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obj_size += 8; /* ctxdma header */
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} else {
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/* 1 entire VM page table */
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aper_size = (512 * 1024 * 1024);
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obj_size = (aper_size >> NV_CTXDMA_PAGE_SHIFT) * 8;
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}
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if ((ret = nouveau_gpuobj_new(dev, -1, obj_size, 16,
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NVOBJ_FLAG_ALLOW_NO_REFS |
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &gpuobj))) {
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DRM_ERROR("Error creating sgdma object: %d\n", ret);
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return ret;
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}
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if (dev_priv->card_type < NV_50) {
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dev_priv->gart_info.sg_dummy_page =
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alloc_page(GFP_KERNEL|__GFP_DMA32);
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SetPageLocked(dev_priv->gart_info.sg_dummy_page);
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dev_priv->gart_info.sg_dummy_bus =
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pci_map_page(dev->pdev,
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dev_priv->gart_info.sg_dummy_page, 0,
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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/* Maybe use NV_DMA_TARGET_AGP for PCIE? NVIDIA do this, and
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* confirmed to work on c51. Perhaps means NV_DMA_TARGET_PCIE
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* on those cards? */
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INSTANCE_WR(gpuobj, 0, NV_CLASS_DMA_IN_MEMORY |
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(1 << 12) /* PT present */ |
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(0 << 13) /* PT *not* linear */ |
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(NV_DMA_ACCESS_RW << 14) |
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(NV_DMA_TARGET_PCI << 16));
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INSTANCE_WR(gpuobj, 1, aper_size - 1);
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for (i=2; i<2+(aper_size>>12); i++) {
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INSTANCE_WR(gpuobj, i,
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dev_priv->gart_info.sg_dummy_bus | 3);
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}
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} else {
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for (i=0; i<obj_size; i+=8) {
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INSTANCE_WR(gpuobj, (i+0)/4, 0); //x00000010);
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INSTANCE_WR(gpuobj, (i+4)/4, 0); //0x00000004);
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}
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}
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dev_priv->gart_info.type = NOUVEAU_GART_SGDMA;
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dev_priv->gart_info.aper_base = 0;
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dev_priv->gart_info.aper_size = aper_size;
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dev_priv->gart_info.sg_ctxdma = gpuobj;
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return 0;
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}
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void
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nouveau_sgdma_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (dev_priv->gart_info.sg_dummy_page) {
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pci_unmap_page(dev->pdev, dev_priv->gart_info.sg_dummy_bus,
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NV_CTXDMA_PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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unlock_page(dev_priv->gart_info.sg_dummy_page);
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__free_page(dev_priv->gart_info.sg_dummy_page);
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dev_priv->gart_info.sg_dummy_page = NULL;
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dev_priv->gart_info.sg_dummy_bus = 0;
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}
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nouveau_gpuobj_del(dev, &dev_priv->gart_info.sg_ctxdma);
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}
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int
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nouveau_sgdma_nottm_hack_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct drm_ttm_backend *be;
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struct drm_scatter_gather sgreq;
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int ret;
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dev_priv->gart_info.sg_be = nouveau_sgdma_init_ttm(dev);
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if (!dev_priv->gart_info.sg_be)
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return -ENOMEM;
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be = dev_priv->gart_info.sg_be;
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/* Hack the aperture size down to the amount of system memory
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* we're going to bind into it.
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*/
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if (dev_priv->gart_info.aper_size > 32*1024*1024)
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dev_priv->gart_info.aper_size = 32*1024*1024;
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sgreq.size = dev_priv->gart_info.aper_size;
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if ((ret = drm_sg_alloc(dev, &sgreq))) {
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DRM_ERROR("drm_sg_alloc failed: %d\n", ret);
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return ret;
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}
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dev_priv->gart_info.sg_handle = sgreq.handle;
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if ((ret = be->func->populate(be, dev->sg->pages, dev->sg->pagelist))) {
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DRM_ERROR("failed populate: %d\n", ret);
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return ret;
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}
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if ((ret = be->func->bind(be, 0, 0))) {
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DRM_ERROR("failed bind: %d\n", ret);
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return ret;
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}
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return 0;
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}
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void
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nouveau_sgdma_nottm_hack_takedown(struct drm_device *dev)
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{
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}
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