326 lines
9.0 KiB
C
326 lines
9.0 KiB
C
/****************************************************************************
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* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* XGI AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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***************************************************************************/
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#include "xgi_drv.h"
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#include "xgi_regs.h"
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#include "xgi_misc.h"
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#include "xgi_cmdlist.h"
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static void xgi_emit_flush(struct xgi_info * info, bool stop);
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static void xgi_emit_nop(struct xgi_info * info);
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static unsigned int get_batch_command(enum xgi_batch_type type);
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static void triggerHWCommandList(struct xgi_info * info);
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static void xgi_cmdlist_reset(struct xgi_info * info);
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/**
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* Graphic engine register (2d/3d) acessing interface
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*/
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static inline void dwWriteReg(struct drm_map * map, u32 addr, u32 data)
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{
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#ifdef XGI_MMIO_DEBUG
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DRM_INFO("mmio_map->handle = 0x%p, addr = 0x%x, data = 0x%x\n",
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map->handle, addr, data);
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#endif
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DRM_WRITE32(map, addr, data);
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}
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int xgi_cmdlist_initialize(struct xgi_info * info, size_t size,
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struct drm_file * filp)
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{
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struct xgi_mem_alloc mem_alloc = {
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.location = XGI_MEMLOC_NON_LOCAL,
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.size = size,
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};
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int err;
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err = xgi_alloc(info, &mem_alloc, filp);
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if (err) {
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return err;
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}
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info->cmdring.ptr = xgi_find_pcie_virt(info, mem_alloc.hw_addr);
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info->cmdring.size = mem_alloc.size;
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info->cmdring.ring_hw_base = mem_alloc.hw_addr;
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info->cmdring.last_ptr = NULL;
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info->cmdring.ring_offset = 0;
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return 0;
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}
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/**
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* get_batch_command - Get the command ID for the current begin type.
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* @type: Type of the current batch
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*
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* See section 3.2.2 "Begin" (page 15) of the 3D SPG.
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*
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* This function assumes that @type is on the range [0,3].
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*/
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unsigned int get_batch_command(enum xgi_batch_type type)
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{
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static const unsigned int ports[4] = {
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0x30 >> 2, 0x40 >> 2, 0x50 >> 2, 0x20 >> 2
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};
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return ports[type];
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}
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int xgi_submit_cmdlist(struct drm_device * dev, void * data,
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struct drm_file * filp)
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{
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struct xgi_info *const info = dev->dev_private;
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const struct xgi_cmd_info *const pCmdInfo =
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(struct xgi_cmd_info *) data;
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const unsigned int cmd = get_batch_command(pCmdInfo->type);
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u32 begin[4];
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begin[0] = (cmd << 24) | BEGIN_VALID_MASK
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| (BEGIN_BEGIN_IDENTIFICATION_MASK & info->next_sequence);
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begin[1] = BEGIN_LINK_ENABLE_MASK | pCmdInfo->size;
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begin[2] = pCmdInfo->hw_addr >> 4;
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begin[3] = 0;
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if (info->cmdring.last_ptr == NULL) {
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const unsigned int portOffset = BASE_3D_ENG + (cmd << 2);
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/* Enable PCI Trigger Mode
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*/
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dwWriteReg(info->mmio_map,
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BASE_3D_ENG + M2REG_AUTO_LINK_SETTING_ADDRESS,
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(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) |
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M2REG_CLEAR_COUNTERS_MASK | 0x08 |
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M2REG_PCI_TRIGGER_MODE_MASK);
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dwWriteReg(info->mmio_map,
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BASE_3D_ENG + M2REG_AUTO_LINK_SETTING_ADDRESS,
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(M2REG_AUTO_LINK_SETTING_ADDRESS << 22) | 0x08 |
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M2REG_PCI_TRIGGER_MODE_MASK);
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/* Send PCI begin command
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*/
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dwWriteReg(info->mmio_map, portOffset, begin[0]);
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dwWriteReg(info->mmio_map, portOffset + 4, begin[1]);
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dwWriteReg(info->mmio_map, portOffset + 8, begin[2]);
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dwWriteReg(info->mmio_map, portOffset + 12, begin[3]);
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} else {
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DRM_DEBUG("info->cmdring.last_ptr != NULL\n");
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if (pCmdInfo->type == BTYPE_3D) {
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xgi_emit_flush(info, false);
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}
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info->cmdring.last_ptr[1] = cpu_to_le32(begin[1]);
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info->cmdring.last_ptr[2] = cpu_to_le32(begin[2]);
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info->cmdring.last_ptr[3] = cpu_to_le32(begin[3]);
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DRM_WRITEMEMORYBARRIER();
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info->cmdring.last_ptr[0] = cpu_to_le32(begin[0]);
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triggerHWCommandList(info);
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}
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info->cmdring.last_ptr = xgi_find_pcie_virt(info, pCmdInfo->hw_addr);
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return 0;
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}
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/*
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state: 0 - console
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1 - graphic
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2 - fb
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3 - logout
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*/
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int xgi_state_change(struct xgi_info * info, unsigned int to,
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unsigned int from)
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{
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#define STATE_CONSOLE 0
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#define STATE_GRAPHIC 1
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#define STATE_FBTERM 2
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#define STATE_LOGOUT 3
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#define STATE_REBOOT 4
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#define STATE_SHUTDOWN 5
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if ((from == STATE_GRAPHIC) && (to == STATE_CONSOLE)) {
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DRM_INFO("Leaving graphical mode (probably VT switch)\n");
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} else if ((from == STATE_CONSOLE) && (to == STATE_GRAPHIC)) {
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DRM_INFO("Entering graphical mode (probably VT switch)\n");
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xgi_cmdlist_reset(info);
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} else if ((from == STATE_GRAPHIC)
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&& ((to == STATE_LOGOUT)
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|| (to == STATE_REBOOT)
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|| (to == STATE_SHUTDOWN))) {
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DRM_INFO("Leaving graphical mode (probably X shutting down)\n");
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} else {
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DRM_ERROR("Invalid state change.\n");
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return -EINVAL;
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}
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return 0;
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}
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int xgi_state_change_ioctl(struct drm_device * dev, void * data,
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struct drm_file * filp)
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{
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struct xgi_state_info *const state =
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(struct xgi_state_info *) data;
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struct xgi_info *info = dev->dev_private;
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return xgi_state_change(info, state->_toState, state->_fromState);
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}
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void xgi_cmdlist_reset(struct xgi_info * info)
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{
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info->cmdring.last_ptr = NULL;
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info->cmdring.ring_offset = 0;
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}
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void xgi_cmdlist_cleanup(struct xgi_info * info)
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{
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if (info->cmdring.ring_hw_base != 0) {
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/* If command lists have been issued, terminate the command
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* list chain with a flush command.
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*/
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if (info->cmdring.last_ptr != NULL) {
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xgi_emit_flush(info, false);
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xgi_emit_nop(info);
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}
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xgi_waitfor_pci_idle(info);
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(void) memset(&info->cmdring, 0, sizeof(info->cmdring));
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}
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}
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static void triggerHWCommandList(struct xgi_info * info)
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{
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static unsigned int s_triggerID = 1;
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dwWriteReg(info->mmio_map,
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BASE_3D_ENG + M2REG_PCI_TRIGGER_REGISTER_ADDRESS,
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0x05000000 + (0x0ffff & s_triggerID++));
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}
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/**
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* Emit a flush to the CRTL command stream.
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* @info XGI info structure
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*
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* This function assumes info->cmdring.ptr is non-NULL.
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*/
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void xgi_emit_flush(struct xgi_info * info, bool stop)
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{
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const u32 flush_command[8] = {
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((0x10 << 24)
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| (BEGIN_BEGIN_IDENTIFICATION_MASK & info->next_sequence)),
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BEGIN_LINK_ENABLE_MASK | (0x00004),
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0x00000000, 0x00000000,
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/* Flush the 2D engine with the default 32 clock delay.
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*/
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M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK,
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M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK,
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M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK,
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M2REG_FLUSH_ENGINE_COMMAND | M2REG_FLUSH_2D_ENGINE_MASK,
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};
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const unsigned int flush_size = sizeof(flush_command);
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u32 *batch_addr;
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u32 hw_addr;
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unsigned int i;
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/* check buf is large enough to contain a new flush batch */
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if ((info->cmdring.ring_offset + flush_size) >= info->cmdring.size) {
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info->cmdring.ring_offset = 0;
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}
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hw_addr = info->cmdring.ring_hw_base
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+ info->cmdring.ring_offset;
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batch_addr = info->cmdring.ptr
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+ (info->cmdring.ring_offset / 4);
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for (i = 0; i < (flush_size / 4); i++) {
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batch_addr[i] = cpu_to_le32(flush_command[i]);
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}
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if (stop) {
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*batch_addr |= cpu_to_le32(BEGIN_STOP_STORE_CURRENT_POINTER_MASK);
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}
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info->cmdring.last_ptr[1] = cpu_to_le32(BEGIN_LINK_ENABLE_MASK | (flush_size / 4));
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info->cmdring.last_ptr[2] = cpu_to_le32(hw_addr >> 4);
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info->cmdring.last_ptr[3] = 0;
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DRM_WRITEMEMORYBARRIER();
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info->cmdring.last_ptr[0] = cpu_to_le32((get_batch_command(BTYPE_CTRL) << 24)
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| (BEGIN_VALID_MASK));
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triggerHWCommandList(info);
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info->cmdring.ring_offset += flush_size;
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info->cmdring.last_ptr = batch_addr;
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}
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/**
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* Emit an empty command to the CRTL command stream.
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* @info XGI info structure
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*
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* This function assumes info->cmdring.ptr is non-NULL. In addition, since
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* this function emits a command that does not have linkage information,
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* it sets info->cmdring.ptr to NULL.
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*/
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void xgi_emit_nop(struct xgi_info * info)
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{
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info->cmdring.last_ptr[1] = cpu_to_le32(BEGIN_LINK_ENABLE_MASK
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| (BEGIN_BEGIN_IDENTIFICATION_MASK & info->next_sequence));
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info->cmdring.last_ptr[2] = 0;
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info->cmdring.last_ptr[3] = 0;
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DRM_WRITEMEMORYBARRIER();
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info->cmdring.last_ptr[0] = cpu_to_le32((get_batch_command(BTYPE_CTRL) << 24)
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| (BEGIN_VALID_MASK));
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triggerHWCommandList(info);
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info->cmdring.last_ptr = NULL;
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}
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void xgi_emit_irq(struct xgi_info * info)
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{
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if (info->cmdring.last_ptr == NULL)
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return;
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xgi_emit_flush(info, true);
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}
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