321 lines
8.8 KiB
C
321 lines
8.8 KiB
C
/*
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* Copyright 2007 Dave Airlie
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* Copyright 2007 Jérôme Glisse
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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/*
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* Authors:
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* Dave Airlie <airlied@linux.ie>
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* Jerome Glisse <glisse@freedesktop.org>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "radeon_ms.h"
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#define GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
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#define GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
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#define GMC_BRUSH_NONE (15 << 4)
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#define GMC_SRC_DATATYPE_COLOR (3 << 12)
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#define ROP3_S 0x00cc0000
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#define DP_SRC_SOURCE_MEMORY (2 << 24)
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#define GMC_CLR_CMP_CNTL_DIS (1 << 28)
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#define GMC_WR_MSK_DIS (1 << 30)
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void radeon_ms_bo_copy_blit(struct drm_device *dev,
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uint32_t src_offset,
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uint32_t dst_offset,
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uint32_t pages)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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uint32_t num_pages, stride, c;
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uint32_t offset_inc = 0;
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uint32_t cmd[7];
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if (!dev_priv) {
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return;
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}
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/* radeon limited to 16320=255*64 bytes per row so copy at
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* most 2 pages */
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num_pages = 2;
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stride = ((num_pages * PAGE_SIZE) / 64) & 0xff;
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while(pages > 0) {
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if (num_pages > pages) {
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num_pages = pages;
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stride = ((num_pages * PAGE_SIZE) / 64) & 0xff;
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}
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c = pages / num_pages;
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if (c >= 8192) {
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c = 8191;
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}
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cmd[0] = CP_PACKET3(PACKET3_OPCODE_BITBLT, 5);
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cmd[1] = GMC_SRC_PITCH_OFFSET_CNTL |
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GMC_DST_PITCH_OFFSET_CNTL |
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GMC_BRUSH_NONE |
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(0x6 << 8) |
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GMC_SRC_DATATYPE_COLOR |
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ROP3_S |
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DP_SRC_SOURCE_MEMORY |
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GMC_CLR_CMP_CNTL_DIS |
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GMC_WR_MSK_DIS;
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cmd[2] = (stride << 22) | (src_offset >> 10);
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cmd[3] = (stride << 22) | (dst_offset >> 10);
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cmd[4] = (0 << 16) | 0;
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cmd[5] = (0 << 16) | 0;
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cmd[6] = ((stride * 16) << 16) | c;
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radeon_ms_ring_emit(dev, cmd, 7);
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offset_inc = num_pages * c * PAGE_SIZE;
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src_offset += offset_inc;
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dst_offset += offset_inc;
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pages -= num_pages * c;
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}
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/* wait for 2d engine to go busy so wait_until stall */
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for (c = 0; c < dev_priv->usec_timeout; c++) {
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uint32_t status = MMIO_R(RBBM_STATUS);
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if ((RBBM_STATUS__E2_BUSY & status) ||
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(RBBM_STATUS__CBA2D_BUSY & status)) {
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DRM_INFO("[radeon_ms] RBBM_STATUS 0x%08X\n", status);
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break;
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}
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DRM_UDELAY(1);
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}
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/* Sync everything up */
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cmd[0] = CP_PACKET0(WAIT_UNTIL, 0);
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cmd[1] = WAIT_UNTIL__WAIT_2D_IDLECLEAN |
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WAIT_UNTIL__WAIT_HOST_IDLECLEAN;
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radeon_ms_ring_emit(dev, cmd, 2);
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return;
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}
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static int radeon_ms_bo_move_blit(struct drm_buffer_object *bo,
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int evict, int no_wait,
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struct drm_bo_mem_reg *new_mem)
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{
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struct drm_device *dev = bo->dev;
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struct drm_bo_mem_reg *old_mem = &bo->mem;
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uint32_t gpu_src_addr;
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uint32_t gpu_dst_addr;
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int ret;
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ret = radeon_ms_bo_get_gpu_addr(dev, old_mem, &gpu_src_addr);
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if (ret) {
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return ret;
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}
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ret = radeon_ms_bo_get_gpu_addr(dev, new_mem, &gpu_dst_addr);
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if (ret) {
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return ret;
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}
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radeon_ms_bo_copy_blit(bo->dev,
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gpu_src_addr,
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gpu_dst_addr,
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new_mem->num_pages);
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ret = drm_bo_move_accel_cleanup(bo, evict, no_wait, 0,
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DRM_FENCE_TYPE_EXE |
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DRM_RADEON_FENCE_TYPE_RW,
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DRM_RADEON_FENCE_FLAG_FLUSHED,
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new_mem);
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return ret;
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}
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static int radeon_ms_bo_move_flip(struct drm_buffer_object *bo,
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int evict, int no_wait,
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struct drm_bo_mem_reg *new_mem)
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{
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struct drm_device *dev = bo->dev;
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struct drm_bo_mem_reg tmp_mem;
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int ret;
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tmp_mem = *new_mem;
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tmp_mem.mm_node = NULL;
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tmp_mem.flags = DRM_BO_FLAG_MEM_TT |
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DRM_BO_FLAG_CACHED |
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DRM_BO_FLAG_FORCE_CACHING;
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ret = drm_bo_mem_space(bo, &tmp_mem, no_wait);
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if (ret) {
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return ret;
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}
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ret = drm_ttm_bind(bo->ttm, &tmp_mem);
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if (ret) {
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goto out_cleanup;
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}
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ret = radeon_ms_bo_move_blit(bo, 1, no_wait, &tmp_mem);
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if (ret) {
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goto out_cleanup;
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}
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ret = drm_bo_move_ttm(bo, evict, no_wait, new_mem);
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out_cleanup:
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if (tmp_mem.mm_node) {
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mutex_lock(&dev->struct_mutex);
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if (tmp_mem.mm_node != bo->pinned_node)
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drm_mm_put_block(tmp_mem.mm_node);
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tmp_mem.mm_node = NULL;
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mutex_unlock(&dev->struct_mutex);
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}
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return ret;
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}
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int radeon_ms_bo_get_gpu_addr(struct drm_device *dev,
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struct drm_bo_mem_reg *mem,
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uint32_t *gpu_addr)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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*gpu_addr = mem->mm_node->start << PAGE_SHIFT;
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switch (mem->flags & DRM_BO_MASK_MEM) {
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case DRM_BO_FLAG_MEM_TT:
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*gpu_addr += dev_priv->gpu_gart_start;
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DRM_INFO("[radeon_ms] GPU TT: 0x%08X\n", *gpu_addr);
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break;
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case DRM_BO_FLAG_MEM_VRAM:
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*gpu_addr += dev_priv->gpu_vram_start;
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DRM_INFO("[radeon_ms] GPU VRAM: 0x%08X\n", *gpu_addr);
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break;
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default:
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DRM_ERROR("[radeon_ms] memory not accessible by GPU\n");
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return -EINVAL;
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}
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return 0;
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}
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int radeon_ms_bo_move(struct drm_buffer_object *bo, int evict,
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int no_wait, struct drm_bo_mem_reg *new_mem)
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{
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struct drm_bo_mem_reg *old_mem = &bo->mem;
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if (old_mem->mem_type == DRM_BO_MEM_LOCAL) {
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return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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} else if (new_mem->mem_type == DRM_BO_MEM_LOCAL) {
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if (radeon_ms_bo_move_flip(bo, evict, no_wait, new_mem))
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return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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} else {
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if (radeon_ms_bo_move_blit(bo, evict, no_wait, new_mem))
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return drm_bo_move_memcpy(bo, evict, no_wait, new_mem);
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}
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return 0;
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}
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struct drm_ttm_backend *radeon_ms_create_ttm_backend(struct drm_device * dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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if (dev_priv && dev_priv->create_ttm)
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return dev_priv->create_ttm(dev);
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return NULL;
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}
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uint64_t radeon_ms_evict_flags(struct drm_buffer_object *bo)
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{
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switch (bo->mem.mem_type) {
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case DRM_BO_MEM_LOCAL:
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case DRM_BO_MEM_TT:
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return DRM_BO_FLAG_MEM_LOCAL;
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case DRM_BO_MEM_VRAM:
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if (bo->mem.num_pages > 128)
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return DRM_BO_MEM_TT;
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else
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return DRM_BO_MEM_LOCAL;
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default:
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return DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_CACHED;
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}
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}
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int radeon_ms_init_mem_type(struct drm_device * dev, uint32_t type,
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struct drm_mem_type_manager * man)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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switch (type) {
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case DRM_BO_MEM_LOCAL:
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man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
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_DRM_FLAG_MEMTYPE_CACHED;
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man->drm_bus_maptype = 0;
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break;
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case DRM_BO_MEM_VRAM:
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man->flags = _DRM_FLAG_MEMTYPE_FIXED |
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_DRM_FLAG_MEMTYPE_MAPPABLE |
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_DRM_FLAG_NEEDS_IOREMAP;
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man->io_addr = NULL;
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man->drm_bus_maptype = _DRM_FRAME_BUFFER;
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man->io_offset = dev_priv->vram.offset;
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man->io_size = dev_priv->vram.size;
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break;
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case DRM_BO_MEM_TT:
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if (!dev_priv->bus_ready) {
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DRM_ERROR("Bus isn't initialized while "
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"intializing TT memory type\n");
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return -EINVAL;
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}
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switch(dev_priv->bus_type) {
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case RADEON_AGP:
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if (!(drm_core_has_AGP(dev) && dev->agp)) {
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DRM_ERROR("AGP is not enabled for memory "
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"type %u\n", (unsigned)type);
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return -EINVAL;
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}
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man->io_offset = dev->agp->agp_info.aper_base;
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man->io_size = dev->agp->agp_info.aper_size *
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1024 * 1024;
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man->io_addr = NULL;
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man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
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_DRM_FLAG_MEMTYPE_CSELECT |
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_DRM_FLAG_NEEDS_IOREMAP;
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man->drm_bus_maptype = _DRM_AGP;
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man->gpu_offset = 0;
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break;
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default:
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man->io_offset = dev_priv->gpu_gart_start;
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man->io_size = dev_priv->gpu_gart_size;
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man->io_addr = NULL;
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man->flags = _DRM_FLAG_MEMTYPE_CSELECT |
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_DRM_FLAG_MEMTYPE_MAPPABLE |
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_DRM_FLAG_MEMTYPE_CMA;
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man->drm_bus_maptype = _DRM_SCATTER_GATHER;
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break;
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}
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break;
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default:
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DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
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return -EINVAL;
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}
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return 0;
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}
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int radeon_ms_invalidate_caches(struct drm_device * dev, uint64_t flags)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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dev_priv->flush_cache(dev);
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return 0;
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}
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void radeon_ms_ttm_flush(struct drm_ttm *ttm)
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{
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if (!ttm)
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return;
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DRM_MEMORYBARRIER();
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}
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