478 lines
11 KiB
C
478 lines
11 KiB
C
/****************************************************************************
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* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* XGI AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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***************************************************************************/
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#include "xgi_drv.h"
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#include "xgi_regs.h"
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#include <linux/delay.h>
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/*
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* irq functions
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*/
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#define STALL_INTERRUPT_RESET_THRESHOLD 0xffff
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static unsigned int s_invalid_begin = 0;
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static bool xgi_validate_signal(struct drm_map * map)
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{
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if (le32_to_cpu(DRM_READ32(map, 0x2800) & 0x001c0000)) {
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u16 check;
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/* Check Read back status */
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DRM_WRITE8(map, 0x235c, 0x80);
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check = le16_to_cpu(DRM_READ16(map, 0x2360));
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if ((check & 0x3f) != ((check & 0x3f00) >> 8)) {
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return FALSE;
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}
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/* Check RO channel */
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DRM_WRITE8(map, 0x235c, 0x83);
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check = le16_to_cpu(DRM_READ16(map, 0x2360));
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if ((check & 0x0f) != ((check & 0xf0) >> 4)) {
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return FALSE;
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}
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/* Check RW channel */
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DRM_WRITE8(map, 0x235c, 0x88);
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check = le16_to_cpu(DRM_READ16(map, 0x2360));
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if ((check & 0x0f) != ((check & 0xf0) >> 4)) {
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return FALSE;
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}
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/* Check RO channel outstanding */
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DRM_WRITE8(map, 0x235c, 0x8f);
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check = le16_to_cpu(DRM_READ16(map, 0x2360));
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if (0 != (check & 0x3ff)) {
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return FALSE;
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}
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/* Check RW channel outstanding */
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DRM_WRITE8(map, 0x235c, 0x90);
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check = le16_to_cpu(DRM_READ16(map, 0x2360));
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if (0 != (check & 0x3ff)) {
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return FALSE;
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}
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/* No pending PCIE request. GE stall. */
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}
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return TRUE;
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}
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static void xgi_ge_hang_reset(struct drm_map * map)
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{
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int time_out = 0xffff;
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DRM_WRITE8(map, 0xb057, 8);
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while (0 != le32_to_cpu(DRM_READ32(map, 0x2800) & 0xf0000000)) {
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while (0 != ((--time_out) & 0xfff))
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/* empty */ ;
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if (0 == time_out) {
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u8 old_3ce;
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u8 old_3cf;
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u8 old_index;
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u8 old_36;
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DRM_INFO("Can not reset back 0x%x!\n",
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le32_to_cpu(DRM_READ32(map, 0x2800)));
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DRM_WRITE8(map, 0xb057, 0);
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/* Have to use 3x5.36 to reset. */
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/* Save and close dynamic gating */
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old_3ce = DRM_READ8(map, 0x3ce);
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DRM_WRITE8(map, 0x3ce, 0x2a);
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old_3cf = DRM_READ8(map, 0x3cf);
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DRM_WRITE8(map, 0x3cf, old_3cf & 0xfe);
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/* Reset GE */
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old_index = DRM_READ8(map, 0x3d4);
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DRM_WRITE8(map, 0x3d4, 0x36);
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old_36 = DRM_READ8(map, 0x3d5);
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DRM_WRITE8(map, 0x3d5, old_36 | 0x10);
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while (0 != ((--time_out) & 0xfff))
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/* empty */ ;
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DRM_WRITE8(map, 0x3d5, old_36);
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DRM_WRITE8(map, 0x3d4, old_index);
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/* Restore dynamic gating */
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DRM_WRITE8(map, 0x3cf, old_3cf);
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DRM_WRITE8(map, 0x3ce, old_3ce);
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break;
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}
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}
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DRM_WRITE8(map, 0xb057, 0);
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}
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bool xgi_ge_irq_handler(struct xgi_info * info)
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{
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const u32 int_status = le32_to_cpu(DRM_READ32(info->mmio_map, 0x2810));
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bool is_support_auto_reset = FALSE;
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/* Check GE on/off */
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if (0 == (0xffffc0f0 & int_status)) {
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if (0 != (0x1000 & int_status)) {
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/* We got GE stall interrupt.
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*/
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DRM_WRITE32(info->mmio_map, 0x2810,
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cpu_to_le32(int_status | 0x04000000));
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if (is_support_auto_reset) {
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static cycles_t last_tick;
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static unsigned continue_int_count = 0;
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/* OE II is busy. */
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if (!xgi_validate_signal(info->mmio_map)) {
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/* Nothing but skip. */
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} else if (0 == continue_int_count++) {
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last_tick = get_cycles();
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} else {
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const cycles_t new_tick = get_cycles();
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if ((new_tick - last_tick) >
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STALL_INTERRUPT_RESET_THRESHOLD) {
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continue_int_count = 0;
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} else if (continue_int_count >= 3) {
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continue_int_count = 0;
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/* GE Hung up, need reset. */
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DRM_INFO("Reset GE!\n");
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xgi_ge_hang_reset(info->mmio_map);
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}
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}
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}
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} else if (0 != (0x1 & int_status)) {
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s_invalid_begin++;
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DRM_WRITE32(info->mmio_map, 0x2810,
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cpu_to_le32((int_status & ~0x01) | 0x04000000));
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}
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return TRUE;
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}
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return FALSE;
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}
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bool xgi_crt_irq_handler(struct xgi_info * info)
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{
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bool ret = FALSE;
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u8 save_3ce = DRM_READ8(info->mmio_map, 0x3ce);
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/* CRT1 interrupt just happened
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*/
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if (IN3CFB(info->mmio_map, 0x37) & 0x01) {
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u8 op3cf_3d;
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u8 op3cf_37;
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/* What happened?
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*/
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op3cf_37 = IN3CFB(info->mmio_map, 0x37);
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/* Clear CRT interrupt
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*/
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op3cf_3d = IN3CFB(info->mmio_map, 0x3d);
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OUT3CFB(info->mmio_map, 0x3d, (op3cf_3d | 0x04));
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OUT3CFB(info->mmio_map, 0x3d, (op3cf_3d & ~0x04));
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ret = TRUE;
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}
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DRM_WRITE8(info->mmio_map, 0x3ce, save_3ce);
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return (ret);
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}
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bool xgi_dvi_irq_handler(struct xgi_info * info)
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{
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bool ret = FALSE;
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const u8 save_3ce = DRM_READ8(info->mmio_map, 0x3ce);
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/* DVI interrupt just happened
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*/
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if (IN3CFB(info->mmio_map, 0x38) & 0x20) {
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const u8 save_3x4 = DRM_READ8(info->mmio_map, 0x3d4);
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u8 op3cf_39;
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u8 op3cf_37;
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u8 op3x5_5a;
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/* What happened?
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*/
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op3cf_37 = IN3CFB(info->mmio_map, 0x37);
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/* Notify BIOS that DVI plug/unplug happened
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*/
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op3x5_5a = IN3X5B(info->mmio_map, 0x5a);
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OUT3X5B(info->mmio_map, 0x5a, op3x5_5a & 0xf7);
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DRM_WRITE8(info->mmio_map, 0x3d4, save_3x4);
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/* Clear DVI interrupt
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*/
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op3cf_39 = IN3CFB(info->mmio_map, 0x39);
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OUT3C5B(info->mmio_map, 0x39, (op3cf_39 & ~0x01));
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OUT3C5B(info->mmio_map, 0x39, (op3cf_39 | 0x01));
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ret = TRUE;
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}
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DRM_WRITE8(info->mmio_map, 0x3ce, save_3ce);
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return (ret);
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}
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static void dump_reg_header(unsigned regbase)
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{
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printk("\n=====xgi_dump_register========0x%x===============\n",
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regbase);
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printk(" 0 1 2 3 4 5 6 7 8 9 a b c d e f\n");
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}
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static void dump_indexed_reg(struct xgi_info * info, unsigned regbase)
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{
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unsigned i, j;
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u8 temp;
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dump_reg_header(regbase);
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for (i = 0; i < 0x10; i++) {
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printk("%1x ", i);
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for (j = 0; j < 0x10; j++) {
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DRM_WRITE8(info->mmio_map, regbase - 1,
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(i * 0x10) + j);
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temp = DRM_READ8(info->mmio_map, regbase);
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printk("%3x", temp);
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}
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printk("\n");
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}
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}
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static void dump_reg(struct xgi_info * info, unsigned regbase, unsigned range)
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{
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unsigned i, j;
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dump_reg_header(regbase);
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for (i = 0; i < range; i++) {
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printk("%1x ", i);
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for (j = 0; j < 0x10; j++) {
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u8 temp = DRM_READ8(info->mmio_map,
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regbase + (i * 0x10) + j);
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printk("%3x", temp);
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}
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printk("\n");
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}
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}
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void xgi_dump_register(struct xgi_info * info)
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{
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dump_indexed_reg(info, 0x3c5);
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dump_indexed_reg(info, 0x3d5);
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dump_indexed_reg(info, 0x3cf);
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dump_reg(info, 0xB000, 0x05);
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dump_reg(info, 0x2200, 0x0B);
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dump_reg(info, 0x2300, 0x07);
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dump_reg(info, 0x2400, 0x10);
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dump_reg(info, 0x2800, 0x10);
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}
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#define WHOLD_GE_STATUS 0x2800
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/* Test everything except the "whole GE busy" bit, the "master engine busy"
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* bit, and the reserved bits [26:21].
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*/
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#define IDLE_MASK ~((1U<<31) | (1U<<28) | (0x3f<<21))
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void xgi_waitfor_pci_idle(struct xgi_info * info)
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{
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unsigned int idleCount = 0;
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u32 old_status = 0;
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unsigned int same_count = 0;
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while (idleCount < 5) {
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const u32 status = DRM_READ32(info->mmio_map, WHOLD_GE_STATUS)
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& IDLE_MASK;
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if (status == old_status) {
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same_count++;
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if ((same_count % 100) == 0) {
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DRM_ERROR("GE status stuck at 0x%08x for %u iterations!\n",
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old_status, same_count);
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}
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} else {
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old_status = status;
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same_count = 0;
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}
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if (status != 0) {
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msleep(1);
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idleCount = 0;
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} else {
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idleCount++;
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}
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}
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}
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void xgi_enable_mmio(struct xgi_info * info)
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{
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u8 protect = 0;
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u8 temp;
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/* Unprotect registers */
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DRM_WRITE8(info->mmio_map, 0x3C4, 0x11);
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protect = DRM_READ8(info->mmio_map, 0x3C5);
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DRM_WRITE8(info->mmio_map, 0x3C5, 0x92);
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DRM_WRITE8(info->mmio_map, 0x3D4, 0x3A);
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temp = DRM_READ8(info->mmio_map, 0x3D5);
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DRM_WRITE8(info->mmio_map, 0x3D5, temp | 0x20);
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/* Enable MMIO */
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DRM_WRITE8(info->mmio_map, 0x3D4, 0x39);
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temp = DRM_READ8(info->mmio_map, 0x3D5);
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DRM_WRITE8(info->mmio_map, 0x3D5, temp | 0x01);
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/* Protect registers */
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OUT3C5B(info->mmio_map, 0x11, protect);
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}
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void xgi_disable_mmio(struct xgi_info * info)
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{
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u8 protect = 0;
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u8 temp;
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/* Unprotect registers */
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DRM_WRITE8(info->mmio_map, 0x3C4, 0x11);
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protect = DRM_READ8(info->mmio_map, 0x3C5);
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DRM_WRITE8(info->mmio_map, 0x3C5, 0x92);
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/* Disable MMIO access */
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DRM_WRITE8(info->mmio_map, 0x3D4, 0x39);
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temp = DRM_READ8(info->mmio_map, 0x3D5);
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DRM_WRITE8(info->mmio_map, 0x3D5, temp & 0xFE);
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/* Protect registers */
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OUT3C5B(info->mmio_map, 0x11, protect);
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}
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void xgi_enable_ge(struct xgi_info * info)
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{
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u8 bOld3cf2a;
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int wait = 0;
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OUT3C5B(info->mmio_map, 0x11, 0x92);
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/* Save and close dynamic gating
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*/
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bOld3cf2a = IN3CFB(info->mmio_map, XGI_MISC_CTRL);
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OUT3CFB(info->mmio_map, XGI_MISC_CTRL, bOld3cf2a & ~EN_GEPWM);
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/* Enable 2D and 3D GE
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*/
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OUT3X5B(info->mmio_map, XGI_GE_CNTL, (GE_ENABLE | GE_ENABLE_3D));
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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/* Reset both 3D and 2D engine
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*/
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OUT3X5B(info->mmio_map, XGI_GE_CNTL,
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(GE_ENABLE | GE_RESET | GE_ENABLE_3D));
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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OUT3X5B(info->mmio_map, XGI_GE_CNTL, (GE_ENABLE | GE_ENABLE_3D));
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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/* Enable 2D engine only
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*/
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OUT3X5B(info->mmio_map, XGI_GE_CNTL, GE_ENABLE);
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/* Enable 2D+3D engine
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*/
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OUT3X5B(info->mmio_map, XGI_GE_CNTL, (GE_ENABLE | GE_ENABLE_3D));
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/* Restore dynamic gating
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*/
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OUT3CFB(info->mmio_map, XGI_MISC_CTRL, bOld3cf2a);
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}
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void xgi_disable_ge(struct xgi_info * info)
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{
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int wait = 0;
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OUT3X5B(info->mmio_map, XGI_GE_CNTL, (GE_ENABLE | GE_ENABLE_3D));
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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/* Reset both 3D and 2D engine
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*/
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OUT3X5B(info->mmio_map, XGI_GE_CNTL,
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(GE_ENABLE | GE_RESET | GE_ENABLE_3D));
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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OUT3X5B(info->mmio_map, XGI_GE_CNTL, (GE_ENABLE | GE_ENABLE_3D));
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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/* Disable 2D engine and 3D engine.
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*/
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OUT3X5B(info->mmio_map, XGI_GE_CNTL, 0);
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}
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