340 lines
8.6 KiB
C
340 lines
8.6 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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struct nv50_fifo_priv {
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struct nouveau_gpuobj_ref *thingo[2];
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int cur_thingo;
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};
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#define IS_G80 ((dev_priv->chipset & 0xf0) == 0x50)
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static void
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nv50_fifo_init_thingo(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
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struct nouveau_gpuobj_ref *cur;
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int i, nr;
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DRM_DEBUG("\n");
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cur = priv->thingo[priv->cur_thingo];
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priv->cur_thingo = !priv->cur_thingo;
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/* We never schedule channel 0 or 127 */
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for (i = 1, nr = 0; i < 127; i++) {
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if (dev_priv->fifos[i]) {
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INSTANCE_WR(cur->gpuobj, nr++, i);
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}
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}
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NV_WRITE(0x32f4, cur->instance >> 12);
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NV_WRITE(0x32ec, nr);
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NV_WRITE(0x2500, 0x101);
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}
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static int
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nv50_fifo_channel_enable(struct drm_device *dev, int channel, int nt)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_channel *chan = dev_priv->fifos[channel];
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uint32_t inst;
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DRM_DEBUG("ch%d\n", channel);
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if (!chan->ramfc)
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return -EINVAL;
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if (IS_G80) inst = chan->ramfc->instance >> 12;
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else inst = chan->ramfc->instance >> 8;
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NV_WRITE(NV50_PFIFO_CTX_TABLE(channel),
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inst | NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED);
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if (!nt) nv50_fifo_init_thingo(dev);
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return 0;
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}
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static void
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nv50_fifo_channel_disable(struct drm_device *dev, int channel, int nt)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t inst;
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DRM_DEBUG("ch%d, nt=%d\n", channel, nt);
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if (IS_G80) inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80;
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else inst = NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84;
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NV_WRITE(NV50_PFIFO_CTX_TABLE(channel), inst);
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if (!nt) nv50_fifo_init_thingo(dev);
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}
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static void
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nv50_fifo_init_reset(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t pmc_e = NV_PMC_ENABLE_PFIFO;
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DRM_DEBUG("\n");
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NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) & ~pmc_e);
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NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) | pmc_e);
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}
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static void
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nv50_fifo_init_intr(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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DRM_DEBUG("\n");
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NV_WRITE(NV03_PFIFO_INTR_0, 0xFFFFFFFF);
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NV_WRITE(NV03_PFIFO_INTR_EN_0, 0xFFFFFFFF);
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}
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static void
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nv50_fifo_init_context_table(struct drm_device *dev)
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{
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int i;
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DRM_DEBUG("\n");
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for (i = 0; i < NV50_PFIFO_CTX_TABLE__SIZE; i++)
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nv50_fifo_channel_disable(dev, i, 1);
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nv50_fifo_init_thingo(dev);
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}
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static void
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nv50_fifo_init_regs__nv(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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DRM_DEBUG("\n");
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NV_WRITE(0x250c, 0x6f3cfc34);
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}
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static void
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nv50_fifo_init_regs(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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DRM_DEBUG("\n");
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NV_WRITE(0x2500, 0);
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NV_WRITE(0x3250, 0);
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NV_WRITE(0x3220, 0);
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NV_WRITE(0x3204, 0);
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NV_WRITE(0x3210, 0);
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NV_WRITE(0x3270, 0);
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/* Enable dummy channels setup by nv50_instmem.c */
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nv50_fifo_channel_enable(dev, 0, 1);
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nv50_fifo_channel_enable(dev, 127, 1);
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}
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int
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nv50_fifo_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_fifo_priv *priv;
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int ret;
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DRM_DEBUG("\n");
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priv = drm_calloc(1, sizeof(*priv), DRM_MEM_DRIVER);
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if (!priv)
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return -ENOMEM;
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dev_priv->Engine.fifo.priv = priv;
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nv50_fifo_init_reset(dev);
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nv50_fifo_init_intr(dev);
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ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[0]);
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if (ret) {
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DRM_ERROR("error creating thingo0: %d\n", ret);
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return ret;
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}
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ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 128*4, 0x1000,
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NVOBJ_FLAG_ZERO_ALLOC, &priv->thingo[1]);
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if (ret) {
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DRM_ERROR("error creating thingo1: %d\n", ret);
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return ret;
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}
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nv50_fifo_init_context_table(dev);
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nv50_fifo_init_regs__nv(dev);
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nv50_fifo_init_regs(dev);
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return 0;
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}
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void
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nv50_fifo_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nv50_fifo_priv *priv = dev_priv->Engine.fifo.priv;
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DRM_DEBUG("\n");
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if (!priv)
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return;
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nouveau_gpuobj_ref_del(dev, &priv->thingo[0]);
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nouveau_gpuobj_ref_del(dev, &priv->thingo[1]);
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dev_priv->Engine.fifo.priv = NULL;
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drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER);
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}
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int
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nv50_fifo_channel_id(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
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NV50_PFIFO_CACHE1_PUSH1_CHID_MASK);
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}
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int
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nv50_fifo_create_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramfc = NULL;
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int ret;
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DRM_DEBUG("ch%d\n", chan->id);
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if (IS_G80) {
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uint32_t ramfc_offset = chan->ramin->gpuobj->im_pramin->start;
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uint32_t vram_offset = chan->ramin->gpuobj->im_backing->start;
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ret = nouveau_gpuobj_new_fake(dev, ramfc_offset, vram_offset,
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0x100, NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE, &ramfc,
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&chan->ramfc);
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if (ret)
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return ret;
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} else {
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 0x100, 256,
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NVOBJ_FLAG_ZERO_ALLOC |
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NVOBJ_FLAG_ZERO_FREE,
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&chan->ramfc);
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if (ret)
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return ret;
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ramfc = chan->ramfc->gpuobj;
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}
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INSTANCE_WR(ramfc, 0x48/4, chan->pushbuf->instance >> 4);
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INSTANCE_WR(ramfc, 0x80/4, (0xc << 24) | (chan->ramht->instance >> 4));
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INSTANCE_WR(ramfc, 0x3c/4, 0x000f0078); /* fetch? */
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INSTANCE_WR(ramfc, 0x44/4, 0x2101ffff);
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INSTANCE_WR(ramfc, 0x60/4, 0x7fffffff);
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INSTANCE_WR(ramfc, 0x10/4, 0x00000000);
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INSTANCE_WR(ramfc, 0x08/4, 0x00000000);
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INSTANCE_WR(ramfc, 0x40/4, 0x00000000);
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INSTANCE_WR(ramfc, 0x50/4, 0x2039b2e0);
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INSTANCE_WR(ramfc, 0x54/4, 0x000f0000);
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INSTANCE_WR(ramfc, 0x7c/4, 0x30000001);
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INSTANCE_WR(ramfc, 0x78/4, 0x00000000);
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INSTANCE_WR(ramfc, 0x4c/4, chan->pushbuf_mem->size - 1);
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if (!IS_G80) {
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INSTANCE_WR(chan->ramin->gpuobj, 0, chan->id);
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INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance);
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INSTANCE_WR(ramfc, 0x88/4, 0x3d520); /* some vram addy >> 10 */
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INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12);
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}
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ret = nv50_fifo_channel_enable(dev, chan->id, 0);
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if (ret) {
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DRM_ERROR("error enabling ch%d: %d\n", chan->id, ret);
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nouveau_gpuobj_ref_del(dev, &chan->ramfc);
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return ret;
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}
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return 0;
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}
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void
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nv50_fifo_destroy_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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DRM_DEBUG("ch%d\n", chan->id);
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nv50_fifo_channel_disable(dev, chan->id, 0);
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/* Dummy channel, also used on ch 127 */
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if (chan->id == 0)
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nv50_fifo_channel_disable(dev, 127, 0);
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nouveau_gpuobj_ref_del(dev, &chan->ramfc);
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}
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int
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nv50_fifo_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramfc = chan->ramfc->gpuobj;
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DRM_DEBUG("ch%d\n", chan->id);
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/*XXX: incomplete, only touches the regs that NV does */
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NV_WRITE(0x3244, 0);
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NV_WRITE(0x3240, 0);
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NV_WRITE(0x3224, INSTANCE_RD(ramfc, 0x3c/4));
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NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, INSTANCE_RD(ramfc, 0x48/4));
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NV_WRITE(0x3234, INSTANCE_RD(ramfc, 0x4c/4));
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NV_WRITE(0x3254, 1);
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NV_WRITE(NV03_PFIFO_RAMHT, INSTANCE_RD(ramfc, 0x80/4));
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if (!IS_G80) {
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NV_WRITE(0x340c, INSTANCE_RD(ramfc, 0x88/4));
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NV_WRITE(0x3410, INSTANCE_RD(ramfc, 0x98/4));
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}
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NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, chan->id | (1<<16));
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return 0;
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}
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int
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nv50_fifo_save_context(struct nouveau_channel *chan)
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{
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DRM_DEBUG("ch%d\n", chan->id);
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DRM_ERROR("stub!\n");
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return 0;
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}
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