343 lines
11 KiB
C
343 lines
11 KiB
C
/*
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* Copyright © 2018 NVIDIA Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <errno.h>
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#include <string.h>
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#include "private.h"
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#include "tegra.h"
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#include "vic.h"
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#include "vic42.h"
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struct vic42 {
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struct vic base;
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struct {
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struct drm_tegra_mapping *map;
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struct drm_tegra_bo *bo;
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} config;
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struct {
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struct drm_tegra_mapping *map;
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struct drm_tegra_bo *bo;
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} filter;
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};
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static int vic42_fill(struct vic *v, struct vic_image *output,
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unsigned int left, unsigned int top,
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unsigned int right, unsigned int bottom,
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unsigned int alpha, unsigned int red,
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unsigned int green, unsigned int blue)
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{
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struct vic42 *vic = container_of(v, struct vic42, base);
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ConfigStruct *c;
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int err;
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err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
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if (err < 0) {
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fprintf(stderr, "failed to map configuration structure: %s\n",
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strerror(-err));
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return err;
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}
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memset(c, 0, sizeof(*c));
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c->outputConfig.TargetRectTop = top;
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c->outputConfig.TargetRectLeft = left;
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c->outputConfig.TargetRectRight = right;
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c->outputConfig.TargetRectBottom = bottom;
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c->outputConfig.BackgroundAlpha = alpha;
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c->outputConfig.BackgroundR = red;
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c->outputConfig.BackgroundG = green;
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c->outputConfig.BackgroundB = blue;
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c->outputSurfaceConfig.OutPixelFormat = output->format;
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c->outputSurfaceConfig.OutBlkKind = output->kind;
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c->outputSurfaceConfig.OutBlkHeight = 0;
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c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
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c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
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c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
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c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
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c->outputSurfaceConfig.OutChromaWidth = 16383;
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c->outputSurfaceConfig.OutChromaHeight = 16383;
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drm_tegra_bo_unmap(vic->config.bo);
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return 0;
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}
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static int vic42_blit(struct vic *v, struct vic_image *output,
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struct vic_image *input)
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{
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struct vic42 *vic = container_of(v, struct vic42, base);
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SlotSurfaceConfig *surface;
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SlotConfig *slot;
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ConfigStruct *c;
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int err;
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err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
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if (err < 0) {
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fprintf(stderr, "failed to map configuration structure: %s\n",
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strerror(-err));
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return err;
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}
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memset(c, 0, sizeof(*c));
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c->outputConfig.TargetRectTop = 0;
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c->outputConfig.TargetRectLeft = 0;
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c->outputConfig.TargetRectRight = output->width - 1;
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c->outputConfig.TargetRectBottom = output->height - 1;
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c->outputConfig.BackgroundAlpha = 255;
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c->outputConfig.BackgroundR = 1023;
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c->outputConfig.BackgroundG = 1023;
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c->outputConfig.BackgroundB = 1023;
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c->outputSurfaceConfig.OutPixelFormat = output->format;
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c->outputSurfaceConfig.OutBlkKind = output->kind;
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c->outputSurfaceConfig.OutBlkHeight = 0;
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c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
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c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
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c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
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c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
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c->outputSurfaceConfig.OutChromaWidth = 16383;
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c->outputSurfaceConfig.OutChromaHeight = 16383;
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slot = &c->slotStruct[0].slotConfig;
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slot->SlotEnable = 1;
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slot->CurrentFieldEnable = 1;
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slot->PlanarAlpha = 255;
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slot->ConstantAlpha = 1;
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slot->SourceRectLeft = 0 << 16;
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slot->SourceRectRight = (input->width - 1) << 16;
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slot->SourceRectTop = 0 << 16;
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slot->SourceRectBottom = (input->height - 1) << 16;
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slot->DestRectLeft = 0;
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slot->DestRectRight = output->width - 1;
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slot->DestRectTop = 0;
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slot->DestRectBottom = output->height - 1;
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slot->SoftClampHigh = 1023;
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surface = &c->slotStruct[0].slotSurfaceConfig;
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surface->SlotPixelFormat = input->format;
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surface->SlotBlkKind = input->kind;
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surface->SlotBlkHeight = 0; /* XXX */
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surface->SlotCacheWidth = VIC_CACHE_WIDTH_64Bx4; /* XXX */
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surface->SlotSurfaceWidth = input->width - 1;
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surface->SlotSurfaceHeight = input->height - 1;
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surface->SlotLumaWidth = input->stride - 1;
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surface->SlotLumaHeight = input->height - 1;
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surface->SlotChromaWidth = 16383;
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surface->SlotChromaHeight = 16383;
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drm_tegra_bo_unmap(vic->config.bo);
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return 0;
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}
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static int vic42_flip(struct vic *v, struct vic_image *output,
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struct vic_image *input)
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{
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struct vic42 *vic = container_of(v, struct vic42, base);
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SlotSurfaceConfig *surface;
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SlotConfig *slot;
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ConfigStruct *c;
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int err;
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err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
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if (err < 0) {
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fprintf(stderr, "failed to map configuration structure: %s\n",
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strerror(-err));
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return err;
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}
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memset(c, 0, sizeof(*c));
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c->outputConfig.TargetRectTop = 0;
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c->outputConfig.TargetRectLeft = 0;
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c->outputConfig.TargetRectRight = output->width - 1;
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c->outputConfig.TargetRectBottom = output->height - 1;
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c->outputConfig.BackgroundAlpha = 255;
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c->outputConfig.BackgroundR = 1023;
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c->outputConfig.BackgroundG = 1023;
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c->outputConfig.BackgroundB = 1023;
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c->outputConfig.OutputFlipY = 1;
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c->outputSurfaceConfig.OutPixelFormat = output->format;
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c->outputSurfaceConfig.OutBlkKind = output->kind;
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c->outputSurfaceConfig.OutBlkHeight = 0;
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c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
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c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
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c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
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c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
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c->outputSurfaceConfig.OutChromaWidth = 16383;
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c->outputSurfaceConfig.OutChromaHeight = 16383;
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slot = &c->slotStruct[0].slotConfig;
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slot->SlotEnable = 1;
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slot->CurrentFieldEnable = 1;
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slot->PlanarAlpha = 255;
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slot->ConstantAlpha = 1;
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slot->SourceRectLeft = 0 << 16;
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slot->SourceRectRight = (input->width - 1) << 16;
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slot->SourceRectTop = 0 << 16;
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slot->SourceRectBottom = (input->height - 1) << 16;
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slot->DestRectLeft = 0;
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slot->DestRectRight = output->width - 1;
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slot->DestRectTop = 0;
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slot->DestRectBottom = output->height - 1;
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slot->SoftClampHigh = 1023;
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surface = &c->slotStruct[0].slotSurfaceConfig;
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surface->SlotPixelFormat = input->format;
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surface->SlotBlkKind = input->kind;
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surface->SlotBlkHeight = 0; /* XXX */
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surface->SlotCacheWidth = VIC_CACHE_WIDTH_64Bx4; /* XXX */
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surface->SlotSurfaceWidth = input->width - 1;
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surface->SlotSurfaceHeight = input->height - 1;
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surface->SlotLumaWidth = input->stride - 1;
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surface->SlotLumaHeight = input->height - 1;
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surface->SlotChromaWidth = 16383;
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surface->SlotChromaHeight = 16383;
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drm_tegra_bo_unmap(vic->config.bo);
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return 0;
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}
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static int vic42_execute(struct vic *v, struct drm_tegra_pushbuf *pushbuf,
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uint32_t **ptrp, struct vic_image *output,
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struct vic_image **inputs, unsigned int num_inputs)
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{
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struct vic42 *vic = container_of(v, struct vic42, base);
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unsigned int i;
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if (num_inputs > 1)
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return -EINVAL;
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VIC_PUSH_METHOD(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID, 1);
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VIC_PUSH_METHOD(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS, (sizeof(ConfigStruct) / 16) << 16);
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VIC_PUSH_BUFFER(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET, vic->config.map, 0, 0);
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VIC_PUSH_BUFFER(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_SET_FILTER_STRUCT_OFFSET, vic->filter.map, 0, 0);
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VIC_PUSH_BUFFER(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET, output->map, 0, 0);
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for (i = 0; i < num_inputs; i++) {
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uint32_t method = NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE0_LUMA_OFFSET(0) + (i * 3) * 4;
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VIC_PUSH_BUFFER(pushbuf, ptrp, method, inputs[i]->map, 0, 0);
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}
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VIC_PUSH_METHOD(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_EXECUTE, 1 << 8);
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return 0;
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}
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static void vic42_free(struct vic *v)
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{
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struct vic42 *vic = container_of(v, struct vic42, base);
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drm_tegra_channel_unmap(vic->filter.map);
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drm_tegra_bo_unref(vic->filter.bo);
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drm_tegra_channel_unmap(vic->config.map);
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drm_tegra_bo_unref(vic->config.bo);
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drm_tegra_syncpoint_free(v->syncpt);
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free(vic);
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}
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static const struct vic_ops vic42_ops = {
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.fill = vic42_fill,
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.blit = vic42_blit,
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.flip = vic42_flip,
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.execute = vic42_execute,
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.free = vic42_free,
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};
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int vic42_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
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struct vic **vicp)
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{
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struct vic42 *vic;
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void *ptr;
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int err;
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vic = calloc(1, sizeof(*vic));
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if (!vic)
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return -ENOMEM;
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vic->base.drm = drm;
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vic->base.channel = channel;
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vic->base.ops = &vic42_ops;
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vic->base.version = 0x19;
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err = drm_tegra_syncpoint_new(drm, &vic->base.syncpt);
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if (err < 0) {
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fprintf(stderr, "failed to allocate syncpoint: %s\n", strerror(-err));
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return err;
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}
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err = drm_tegra_bo_new(drm, 0, 16384, &vic->config.bo);
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if (err < 0) {
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fprintf(stderr, "failed to allocate configuration structurer: %s\n",
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strerror(-err));
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return err;
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}
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err = drm_tegra_channel_map(channel, vic->config.bo, DRM_TEGRA_CHANNEL_MAP_READ,
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&vic->config.map);
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if (err < 0) {
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fprintf(stderr, "failed to map configuration structure: %s\n",
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strerror(-err));
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return err;
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}
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err = drm_tegra_bo_new(drm, 0, 16384, &vic->filter.bo);
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if (err < 0) {
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fprintf(stderr, "failed to allocate filter buffer: %s\n",
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strerror(-err));
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return err;
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}
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err = drm_tegra_bo_map(vic->filter.bo, &ptr);
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if (err < 0) {
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fprintf(stderr, "failed to map filter buffer: %s\n", strerror(-err));
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return err;
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}
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memset(ptr, 0, 16384);
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drm_tegra_bo_unmap(vic->filter.bo);
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err = drm_tegra_channel_map(channel, vic->filter.bo, DRM_TEGRA_CHANNEL_MAP_READ,
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&vic->filter.map);
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if (err < 0) {
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fprintf(stderr, "failed to map filter buffer: %s\n",
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strerror(-err));
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return err;
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}
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if (vicp)
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*vicp = &vic->base;
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return 0;
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}
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