279 lines
8.5 KiB
C
279 lines
8.5 KiB
C
/*
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* Copyright © 2014 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <errno.h>
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#include <string.h>
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#include "amdgpu.h"
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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#include "xf86drm.h"
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int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
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unsigned size, void *value)
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{
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struct drm_amdgpu_info request;
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memset(&request, 0, sizeof(request));
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request.return_pointer = (uintptr_t)value;
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request.return_size = size;
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request.query = info_id;
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return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
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sizeof(struct drm_amdgpu_info));
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}
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int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
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int32_t *result)
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{
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struct drm_amdgpu_info request;
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memset(&request, 0, sizeof(request));
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request.return_pointer = (uintptr_t)result;
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request.return_size = sizeof(*result);
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request.query = AMDGPU_INFO_CRTC_FROM_ID;
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request.mode_crtc.id = id;
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return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
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sizeof(struct drm_amdgpu_info));
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}
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int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
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unsigned count, uint32_t instance, uint32_t flags,
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uint32_t *values)
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{
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struct drm_amdgpu_info request;
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memset(&request, 0, sizeof(request));
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request.return_pointer = (uintptr_t)values;
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request.return_size = count * sizeof(uint32_t);
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request.query = AMDGPU_INFO_READ_MMR_REG;
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request.read_mmr_reg.dword_offset = dword_offset;
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request.read_mmr_reg.count = count;
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request.read_mmr_reg.instance = instance;
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request.read_mmr_reg.flags = flags;
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return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
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sizeof(struct drm_amdgpu_info));
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}
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int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
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uint32_t *count)
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{
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struct drm_amdgpu_info request;
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memset(&request, 0, sizeof(request));
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request.return_pointer = (uintptr_t)count;
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request.return_size = sizeof(*count);
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request.query = AMDGPU_INFO_HW_IP_COUNT;
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request.query_hw_ip.type = type;
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return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
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sizeof(struct drm_amdgpu_info));
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}
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int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
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unsigned ip_instance,
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struct drm_amdgpu_info_hw_ip *info)
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{
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struct drm_amdgpu_info request;
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memset(&request, 0, sizeof(request));
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request.return_pointer = (uintptr_t)info;
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request.return_size = sizeof(*info);
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request.query = AMDGPU_INFO_HW_IP_INFO;
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request.query_hw_ip.type = type;
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request.query_hw_ip.ip_instance = ip_instance;
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return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
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sizeof(struct drm_amdgpu_info));
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}
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int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
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unsigned ip_instance, unsigned index,
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uint32_t *version, uint32_t *feature)
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{
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struct drm_amdgpu_info request;
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struct drm_amdgpu_info_firmware firmware;
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int r;
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memset(&request, 0, sizeof(request));
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request.return_pointer = (uintptr_t)&firmware;
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request.return_size = sizeof(firmware);
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request.query = AMDGPU_INFO_FW_VERSION;
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request.query_fw.fw_type = fw_type;
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request.query_fw.ip_instance = ip_instance;
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request.query_fw.index = index;
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r = drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request,
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sizeof(struct drm_amdgpu_info));
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if (r)
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return r;
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*version = firmware.ver;
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*feature = firmware.feature;
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return 0;
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}
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int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
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{
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int r, i;
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r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(dev->dev_info),
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&dev->dev_info);
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if (r)
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return r;
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dev->info.asic_id = dev->dev_info.device_id;
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dev->info.chip_rev = dev->dev_info.chip_rev;
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dev->info.chip_external_rev = dev->dev_info.external_rev;
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dev->info.family_id = dev->dev_info.family;
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dev->info.max_engine_clk = dev->dev_info.max_engine_clock;
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dev->info.max_memory_clk = dev->dev_info.max_memory_clock;
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dev->info.gpu_counter_freq = dev->dev_info.gpu_counter_freq;
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dev->info.enabled_rb_pipes_mask = dev->dev_info.enabled_rb_pipes_mask;
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dev->info.rb_pipes = dev->dev_info.num_rb_pipes;
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dev->info.ids_flags = dev->dev_info.ids_flags;
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dev->info.num_hw_gfx_contexts = dev->dev_info.num_hw_gfx_contexts;
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dev->info.num_shader_engines = dev->dev_info.num_shader_engines;
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dev->info.num_shader_arrays_per_engine =
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dev->dev_info.num_shader_arrays_per_engine;
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dev->info.vram_type = dev->dev_info.vram_type;
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dev->info.vram_bit_width = dev->dev_info.vram_bit_width;
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dev->info.ce_ram_size = dev->dev_info.ce_ram_size;
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for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
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unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
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(AMDGPU_INFO_MMR_SH_INDEX_MASK <<
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AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
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r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0,
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&dev->info.backend_disable[i]);
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if (r)
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return r;
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/* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
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dev->info.backend_disable[i] =
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(dev->info.backend_disable[i] >> 16) & 0xff;
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r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
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&dev->info.pa_sc_raster_cfg[i]);
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if (r)
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return r;
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r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
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&dev->info.pa_sc_raster_cfg1[i]);
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if (r)
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return r;
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}
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r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
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dev->info.gb_tile_mode);
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if (r)
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return r;
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r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
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dev->info.gb_macro_tile_mode);
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if (r)
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return r;
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r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
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&dev->info.gb_addr_cfg);
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if (r)
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return r;
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r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
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&dev->info.mc_arb_ramcfg);
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if (r)
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return r;
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dev->info.cu_active_number = dev->dev_info.cu_active_number;
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dev->info.cu_ao_mask = dev->dev_info.cu_ao_mask;
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memcpy(&dev->info.cu_bitmap[0][0], &dev->dev_info.cu_bitmap[0][0], sizeof(dev->info.cu_bitmap));
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/* TODO: info->max_quad_shader_pipes is not set */
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/* TODO: info->avail_quad_shader_pipes is not set */
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/* TODO: info->cache_entries_per_quad_pipe is not set */
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return 0;
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}
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int amdgpu_query_gpu_info(amdgpu_device_handle dev,
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struct amdgpu_gpu_info *info)
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{
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/* Get ASIC info*/
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*info = dev->info;
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return 0;
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}
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int amdgpu_query_heap_info(amdgpu_device_handle dev,
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uint32_t heap,
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uint32_t flags,
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struct amdgpu_heap_info *info)
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{
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struct drm_amdgpu_info_vram_gtt vram_gtt_info = {};
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int r;
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r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_GTT,
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sizeof(vram_gtt_info), &vram_gtt_info);
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if (r)
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return r;
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/* Get heap information */
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switch (heap) {
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case AMDGPU_GEM_DOMAIN_VRAM:
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/* query visible only vram heap */
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if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
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info->heap_size = vram_gtt_info.vram_cpu_accessible_size;
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else /* query total vram heap */
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info->heap_size = vram_gtt_info.vram_size;
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info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
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if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
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r = amdgpu_query_info(dev, AMDGPU_INFO_VIS_VRAM_USAGE,
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sizeof(info->heap_usage),
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&info->heap_usage);
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else
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r = amdgpu_query_info(dev, AMDGPU_INFO_VRAM_USAGE,
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sizeof(info->heap_usage),
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&info->heap_usage);
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if (r)
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return r;
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break;
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case AMDGPU_GEM_DOMAIN_GTT:
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info->heap_size = vram_gtt_info.gtt_size;
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info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
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r = amdgpu_query_info(dev, AMDGPU_INFO_GTT_USAGE,
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sizeof(info->heap_usage),
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&info->heap_usage);
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if (r)
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return r;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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