567 lines
18 KiB
C
567 lines
18 KiB
C
/*
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* Copyright 2005 Stephane Marchesin
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "drm_sarea.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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static int nouveau_init_card_mappings(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int ret;
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/* resource 0 is mmio regs */
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/* resource 1 is linear FB */
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/* resource 2 is RAMIN (mmio regs + 0x1000000) */
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/* resource 6 is bios */
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/* map the mmio regs */
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ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
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drm_get_resource_len(dev, 0),
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_DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
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if (ret) {
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DRM_ERROR("Unable to initialize the mmio mapping (%d). "
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"Please report your setup to " DRIVER_EMAIL "\n",
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ret);
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return 1;
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}
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DRM_DEBUG("regs mapped ok at 0x%lx\n", dev_priv->mmio->offset);
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/* map larger RAMIN aperture on NV40 cards */
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dev_priv->ramin = NULL;
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if (dev_priv->card_type >= NV_40) {
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int ramin_resource = 2;
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if (drm_get_resource_len(dev, ramin_resource) == 0)
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ramin_resource = 3;
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ret = drm_addmap(dev,
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drm_get_resource_start(dev, ramin_resource),
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drm_get_resource_len(dev, ramin_resource),
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_DRM_REGISTERS, _DRM_READ_ONLY,
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&dev_priv->ramin);
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if (ret) {
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DRM_ERROR("Failed to init RAMIN mapping, "
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"limited instance memory available\n");
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dev_priv->ramin = NULL;
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}
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}
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/* On older cards (or if the above failed), create a map covering
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* the BAR0 PRAMIN aperture */
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if (!dev_priv->ramin) {
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ret = drm_addmap(dev,
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drm_get_resource_start(dev, 0) + NV_RAMIN,
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(1*1024*1024),
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_DRM_REGISTERS, _DRM_READ_ONLY,
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&dev_priv->ramin);
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if (ret) {
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DRM_ERROR("Failed to map BAR0 PRAMIN: %d\n", ret);
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return ret;
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}
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}
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return 0;
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}
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static int nouveau_stub_init(struct drm_device *dev) { return 0; }
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static void nouveau_stub_takedown(struct drm_device *dev) {}
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static uint64_t nouveau_stub_timer_read(struct drm_device *dev) { return 0; }
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static int nouveau_init_engine_ptrs(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine = &dev_priv->Engine;
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switch (dev_priv->chipset & 0xf0) {
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case 0x00:
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engine->instmem.init = nv04_instmem_init;
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engine->instmem.takedown= nv04_instmem_takedown;
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engine->instmem.populate = nv04_instmem_populate;
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engine->instmem.clear = nv04_instmem_clear;
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engine->instmem.bind = nv04_instmem_bind;
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engine->instmem.unbind = nv04_instmem_unbind;
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engine->mc.init = nv04_mc_init;
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engine->mc.takedown = nv04_mc_takedown;
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engine->timer.init = nv04_timer_init;
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engine->timer.read = nv04_timer_read;
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engine->timer.takedown = nv04_timer_takedown;
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engine->fb.init = nv04_fb_init;
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engine->fb.takedown = nv04_fb_takedown;
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engine->graph.init = nv04_graph_init;
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engine->graph.takedown = nv04_graph_takedown;
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engine->graph.create_context = nv04_graph_create_context;
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engine->graph.destroy_context = nv04_graph_destroy_context;
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engine->graph.load_context = nv04_graph_load_context;
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engine->graph.save_context = nv04_graph_save_context;
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engine->fifo.init = nouveau_fifo_init;
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engine->fifo.takedown = nouveau_stub_takedown;
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engine->fifo.create_context = nv04_fifo_create_context;
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engine->fifo.destroy_context = nv04_fifo_destroy_context;
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engine->fifo.load_context = nv04_fifo_load_context;
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engine->fifo.save_context = nv04_fifo_save_context;
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break;
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case 0x10:
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engine->instmem.init = nv04_instmem_init;
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engine->instmem.takedown= nv04_instmem_takedown;
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engine->instmem.populate = nv04_instmem_populate;
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engine->instmem.clear = nv04_instmem_clear;
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engine->instmem.bind = nv04_instmem_bind;
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engine->instmem.unbind = nv04_instmem_unbind;
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engine->mc.init = nv04_mc_init;
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engine->mc.takedown = nv04_mc_takedown;
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engine->timer.init = nv04_timer_init;
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engine->timer.read = nv04_timer_read;
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engine->timer.takedown = nv04_timer_takedown;
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engine->fb.init = nv10_fb_init;
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engine->fb.takedown = nv10_fb_takedown;
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engine->graph.init = nv10_graph_init;
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engine->graph.takedown = nv10_graph_takedown;
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engine->graph.create_context = nv10_graph_create_context;
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engine->graph.destroy_context = nv10_graph_destroy_context;
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engine->graph.load_context = nv10_graph_load_context;
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engine->graph.save_context = nv10_graph_save_context;
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engine->fifo.init = nouveau_fifo_init;
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engine->fifo.takedown = nouveau_stub_takedown;
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engine->fifo.create_context = nv10_fifo_create_context;
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engine->fifo.destroy_context = nv10_fifo_destroy_context;
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engine->fifo.load_context = nv10_fifo_load_context;
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engine->fifo.save_context = nv10_fifo_save_context;
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break;
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case 0x20:
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engine->instmem.init = nv04_instmem_init;
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engine->instmem.takedown= nv04_instmem_takedown;
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engine->instmem.populate = nv04_instmem_populate;
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engine->instmem.clear = nv04_instmem_clear;
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engine->instmem.bind = nv04_instmem_bind;
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engine->instmem.unbind = nv04_instmem_unbind;
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engine->mc.init = nv04_mc_init;
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engine->mc.takedown = nv04_mc_takedown;
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engine->timer.init = nv04_timer_init;
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engine->timer.read = nv04_timer_read;
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engine->timer.takedown = nv04_timer_takedown;
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engine->fb.init = nv10_fb_init;
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engine->fb.takedown = nv10_fb_takedown;
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engine->graph.init = nv20_graph_init;
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engine->graph.takedown = nv20_graph_takedown;
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engine->graph.create_context = nv20_graph_create_context;
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engine->graph.destroy_context = nv20_graph_destroy_context;
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engine->graph.load_context = nv20_graph_load_context;
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engine->graph.save_context = nv20_graph_save_context;
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engine->fifo.init = nouveau_fifo_init;
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engine->fifo.takedown = nouveau_stub_takedown;
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engine->fifo.create_context = nv10_fifo_create_context;
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engine->fifo.destroy_context = nv10_fifo_destroy_context;
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engine->fifo.load_context = nv10_fifo_load_context;
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engine->fifo.save_context = nv10_fifo_save_context;
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break;
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case 0x30:
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engine->instmem.init = nv04_instmem_init;
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engine->instmem.takedown= nv04_instmem_takedown;
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engine->instmem.populate = nv04_instmem_populate;
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engine->instmem.clear = nv04_instmem_clear;
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engine->instmem.bind = nv04_instmem_bind;
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engine->instmem.unbind = nv04_instmem_unbind;
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engine->mc.init = nv04_mc_init;
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engine->mc.takedown = nv04_mc_takedown;
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engine->timer.init = nv04_timer_init;
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engine->timer.read = nv04_timer_read;
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engine->timer.takedown = nv04_timer_takedown;
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engine->fb.init = nv10_fb_init;
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engine->fb.takedown = nv10_fb_takedown;
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engine->graph.init = nv30_graph_init;
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engine->graph.takedown = nv30_graph_takedown;
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engine->graph.create_context = nv30_graph_create_context;
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engine->graph.destroy_context = nv30_graph_destroy_context;
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engine->graph.load_context = nv30_graph_load_context;
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engine->graph.save_context = nv30_graph_save_context;
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engine->fifo.init = nouveau_fifo_init;
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engine->fifo.takedown = nouveau_stub_takedown;
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engine->fifo.create_context = nv10_fifo_create_context;
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engine->fifo.destroy_context = nv10_fifo_destroy_context;
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engine->fifo.load_context = nv10_fifo_load_context;
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engine->fifo.save_context = nv10_fifo_save_context;
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break;
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case 0x40:
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engine->instmem.init = nv04_instmem_init;
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engine->instmem.takedown= nv04_instmem_takedown;
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engine->instmem.populate = nv04_instmem_populate;
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engine->instmem.clear = nv04_instmem_clear;
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engine->instmem.bind = nv04_instmem_bind;
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engine->instmem.unbind = nv04_instmem_unbind;
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engine->mc.init = nv40_mc_init;
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engine->mc.takedown = nv40_mc_takedown;
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engine->timer.init = nv04_timer_init;
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engine->timer.read = nv04_timer_read;
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engine->timer.takedown = nv04_timer_takedown;
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engine->fb.init = nv40_fb_init;
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engine->fb.takedown = nv40_fb_takedown;
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engine->graph.init = nv40_graph_init;
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engine->graph.takedown = nv40_graph_takedown;
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engine->graph.create_context = nv40_graph_create_context;
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engine->graph.destroy_context = nv40_graph_destroy_context;
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engine->graph.load_context = nv40_graph_load_context;
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engine->graph.save_context = nv40_graph_save_context;
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engine->fifo.init = nouveau_fifo_init;
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engine->fifo.takedown = nouveau_stub_takedown;
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engine->fifo.create_context = nv40_fifo_create_context;
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engine->fifo.destroy_context = nv40_fifo_destroy_context;
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engine->fifo.load_context = nv40_fifo_load_context;
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engine->fifo.save_context = nv40_fifo_save_context;
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break;
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case 0x50:
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case 0x80: /* gotta love NVIDIA's consistency.. */
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engine->instmem.init = nv50_instmem_init;
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engine->instmem.takedown= nv50_instmem_takedown;
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engine->instmem.populate = nv50_instmem_populate;
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engine->instmem.clear = nv50_instmem_clear;
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engine->instmem.bind = nv50_instmem_bind;
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engine->instmem.unbind = nv50_instmem_unbind;
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engine->mc.init = nv50_mc_init;
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engine->mc.takedown = nv50_mc_takedown;
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engine->timer.init = nouveau_stub_init;
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engine->timer.read = nouveau_stub_timer_read;
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engine->timer.takedown = nouveau_stub_takedown;
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engine->fb.init = nouveau_stub_init;
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engine->fb.takedown = nouveau_stub_takedown;
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engine->graph.init = nv50_graph_init;
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engine->graph.takedown = nv50_graph_takedown;
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engine->graph.create_context = nv50_graph_create_context;
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engine->graph.destroy_context = nv50_graph_destroy_context;
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engine->graph.load_context = nv50_graph_load_context;
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engine->graph.save_context = nv50_graph_save_context;
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engine->fifo.init = nv50_fifo_init;
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engine->fifo.takedown = nv50_fifo_takedown;
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engine->fifo.create_context = nv50_fifo_create_context;
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engine->fifo.destroy_context = nv50_fifo_destroy_context;
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engine->fifo.load_context = nv50_fifo_load_context;
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engine->fifo.save_context = nv50_fifo_save_context;
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break;
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default:
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DRM_ERROR("NV%02x unsupported\n", dev_priv->chipset);
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return 1;
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}
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return 0;
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}
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int
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nouveau_card_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine;
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int ret;
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DRM_DEBUG("prev state = %d\n", dev_priv->init_state);
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if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
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return 0;
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/* Map any PCI resources we need on the card */
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ret = nouveau_init_card_mappings(dev);
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if (ret) return ret;
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/* Determine exact chipset we're running on */
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if (dev_priv->card_type < NV_10)
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dev_priv->chipset = dev_priv->card_type;
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else
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dev_priv->chipset =
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(NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;
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/* Initialise internal driver API hooks */
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ret = nouveau_init_engine_ptrs(dev);
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if (ret) return ret;
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engine = &dev_priv->Engine;
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dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
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INIT_LIST_HEAD(&dev_priv->gpuobj_list);
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/* Initialise instance memory, must happen before mem_init so we
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* know exactly how much VRAM we're able to use for "normal"
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* purposes.
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*/
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ret = engine->instmem.init(dev);
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if (ret) return ret;
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/* Setup the memory manager */
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ret = nouveau_mem_init(dev);
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if (ret) return ret;
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ret = nouveau_gpuobj_init(dev);
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if (ret) return ret;
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/* Parse BIOS tables / Run init tables? */
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/* PMC */
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ret = engine->mc.init(dev);
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if (ret) return ret;
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/* PTIMER */
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ret = engine->timer.init(dev);
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if (ret) return ret;
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/* PFB */
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ret = engine->fb.init(dev);
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if (ret) return ret;
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/* PGRAPH */
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ret = engine->graph.init(dev);
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if (ret) return ret;
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/* PFIFO */
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ret = engine->fifo.init(dev);
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if (ret) return ret;
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/* this call irq_preinstall, register irq handler and
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* call irq_postinstall
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*/
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ret = drm_irq_install(dev);
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if (ret) return ret;
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/* what about PVIDEO/PCRTC/PRAMDAC etc? */
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ret = nouveau_dma_channel_init(dev);
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if (ret) return ret;
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dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
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return 0;
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}
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static void nouveau_card_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_engine *engine = &dev_priv->Engine;
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DRM_DEBUG("prev state = %d\n", dev_priv->init_state);
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if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
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nouveau_dma_channel_takedown(dev);
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engine->fifo.takedown(dev);
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engine->graph.takedown(dev);
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engine->fb.takedown(dev);
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engine->timer.takedown(dev);
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engine->mc.takedown(dev);
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nouveau_sgdma_nottm_hack_takedown(dev);
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nouveau_sgdma_takedown(dev);
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nouveau_gpuobj_takedown(dev);
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nouveau_mem_close(dev);
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engine->instmem.takedown(dev);
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drm_irq_uninstall(dev);
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dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
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}
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}
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/* here a client dies, release the stuff that was allocated for its
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* file_priv */
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void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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nouveau_fifo_cleanup(dev, file_priv);
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nouveau_mem_release(file_priv,dev_priv->fb_heap);
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nouveau_mem_release(file_priv,dev_priv->agp_heap);
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nouveau_mem_release(file_priv,dev_priv->pci_heap);
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}
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/* first module load, setup the mmio/fb mapping */
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int nouveau_firstopen(struct drm_device *dev)
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{
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return 0;
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}
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int nouveau_load(struct drm_device *dev, unsigned long flags)
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{
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struct drm_nouveau_private *dev_priv;
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if (flags==NV_UNKNOWN)
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return -EINVAL;
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dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER);
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if (!dev_priv)
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return -ENOMEM;
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dev_priv->card_type=flags&NOUVEAU_FAMILY;
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dev_priv->flags=flags&NOUVEAU_FLAGS;
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dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
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dev->dev_private = (void *)dev_priv;
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return 0;
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}
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void nouveau_lastclose(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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nouveau_card_takedown(dev);
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if(dev_priv->fb_mtrr>0)
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{
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drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1),nouveau_mem_fb_amount(dev), DRM_MTRR_WC);
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dev_priv->fb_mtrr=0;
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}
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}
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int nouveau_unload(struct drm_device *dev)
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{
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drm_free(dev->dev_private, sizeof(*dev->dev_private), DRM_MEM_DRIVER);
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dev->dev_private = NULL;
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
nouveau_ioctl_card_init(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
return nouveau_card_init(dev);
|
|
}
|
|
|
|
int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct drm_nouveau_getparam *getparam = data;
|
|
|
|
NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
|
|
|
|
switch (getparam->param) {
|
|
case NOUVEAU_GETPARAM_CHIPSET_ID:
|
|
getparam->value = dev_priv->chipset;
|
|
break;
|
|
case NOUVEAU_GETPARAM_PCI_VENDOR:
|
|
getparam->value=dev->pci_vendor;
|
|
break;
|
|
case NOUVEAU_GETPARAM_PCI_DEVICE:
|
|
getparam->value=dev->pci_device;
|
|
break;
|
|
case NOUVEAU_GETPARAM_BUS_TYPE:
|
|
if (drm_device_is_agp(dev))
|
|
getparam->value=NV_AGP;
|
|
else if (drm_device_is_pcie(dev))
|
|
getparam->value=NV_PCIE;
|
|
else
|
|
getparam->value=NV_PCI;
|
|
break;
|
|
case NOUVEAU_GETPARAM_FB_PHYSICAL:
|
|
getparam->value=dev_priv->fb_phys;
|
|
break;
|
|
case NOUVEAU_GETPARAM_AGP_PHYSICAL:
|
|
getparam->value=dev_priv->gart_info.aper_base;
|
|
break;
|
|
case NOUVEAU_GETPARAM_PCI_PHYSICAL:
|
|
if ( dev -> sg )
|
|
getparam->value=(uint64_t) dev->sg->virtual;
|
|
else
|
|
{
|
|
DRM_ERROR("Requested PCIGART address, while no PCIGART was created\n");
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
case NOUVEAU_GETPARAM_FB_SIZE:
|
|
getparam->value=dev_priv->fb_available_size;
|
|
break;
|
|
case NOUVEAU_GETPARAM_AGP_SIZE:
|
|
getparam->value=dev_priv->gart_info.aper_size;
|
|
break;
|
|
default:
|
|
DRM_ERROR("unknown parameter %lld\n", getparam->param);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int nouveau_ioctl_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct drm_nouveau_setparam *setparam = data;
|
|
|
|
NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
|
|
|
|
switch (setparam->param) {
|
|
case NOUVEAU_SETPARAM_CMDBUF_LOCATION:
|
|
switch (setparam->value) {
|
|
case NOUVEAU_MEM_AGP:
|
|
case NOUVEAU_MEM_FB:
|
|
case NOUVEAU_MEM_PCI:
|
|
case NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI_ACCEPTABLE:
|
|
break;
|
|
default:
|
|
DRM_ERROR("invalid CMDBUF_LOCATION value=%lld\n",
|
|
setparam->value);
|
|
return -EINVAL;
|
|
}
|
|
dev_priv->config.cmdbuf.location = setparam->value;
|
|
break;
|
|
case NOUVEAU_SETPARAM_CMDBUF_SIZE:
|
|
dev_priv->config.cmdbuf.size = setparam->value;
|
|
break;
|
|
default:
|
|
DRM_ERROR("unknown parameter %lld\n", setparam->param);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* waits for idle */
|
|
void nouveau_wait_for_idle(struct drm_device *dev)
|
|
{
|
|
struct drm_nouveau_private *dev_priv=dev->dev_private;
|
|
switch(dev_priv->card_type) {
|
|
case NV_03:
|
|
while (NV_READ(NV03_PGRAPH_STATUS));
|
|
break;
|
|
case NV_50:
|
|
break;
|
|
default: {
|
|
/* This stuff is more or less a copy of what is seen
|
|
* in nv28 kmmio dump.
|
|
*/
|
|
uint64_t started = dev_priv->Engine.timer.read(dev);
|
|
uint64_t stopped = started;
|
|
uint32_t status;
|
|
do {
|
|
uint32_t pmc_e = NV_READ(NV03_PMC_ENABLE);
|
|
(void)pmc_e;
|
|
status = NV_READ(NV04_PGRAPH_STATUS);
|
|
if (!status)
|
|
break;
|
|
stopped = dev_priv->Engine.timer.read(dev);
|
|
/* It'll never wrap anyway... */
|
|
} while (stopped - started < 1000000000ULL);
|
|
if (status)
|
|
DRM_ERROR("timed out with status 0x%08x\n",
|
|
status);
|
|
}
|
|
}
|
|
}
|
|
|
|
|