339 lines
8.2 KiB
C
339 lines
8.2 KiB
C
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/****************************************************************************
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* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
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* *
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* All Rights Reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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* *
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
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* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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***************************************************************************/
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#include "xgi_drv.h"
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#include "xgi_regs.h"
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#include "xgi_misc.h"
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static struct xgi_mem_block *xgi_pcie_vertex_block = NULL;
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static struct xgi_mem_block *xgi_pcie_cmdlist_block = NULL;
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static struct xgi_mem_block *xgi_pcie_scratchpad_block = NULL;
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static int xgi_pcie_lut_init(struct xgi_info * info)
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{
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u8 temp = 0;
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int err;
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unsigned i;
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struct drm_scatter_gather request;
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struct drm_sg_mem *sg;
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u32 *lut;
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/* Get current FB aperture size */
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temp = IN3X5B(info->mmio_map, 0x27);
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DRM_INFO("In3x5(0x27): 0x%x \n", temp);
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if (temp & 0x01) { /* 256MB; Jong 06/05/2006; 0x10000000 */
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info->pcie.base = 256 * 1024 * 1024;
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} else { /* 128MB; Jong 06/05/2006; 0x08000000 */
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info->pcie.base = 128 * 1024 * 1024;
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}
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DRM_INFO("info->pcie.base: 0x%lx\n", (unsigned long) info->pcie.base);
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/* Get current lookup table page size */
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temp = DRM_READ8(info->mmio_map, 0xB00C);
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if (temp & 0x04) { /* 8KB */
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info->lutPageSize = 8 * 1024;
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} else { /* 4KB */
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info->lutPageSize = 4 * 1024;
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}
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DRM_INFO("info->lutPageSize: 0x%x \n", info->lutPageSize);
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request.size = info->pcie.size;
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err = drm_sg_alloc(info->dev, & request);
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if (err) {
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DRM_ERROR("cannot allocate PCIE GART backing store! "
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"size = %d\n", info->pcie.size);
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return err;
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}
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sg = info->dev->sg;
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info->lut_handle = drm_pci_alloc(info->dev,
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sizeof(u32) * sg->pages,
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PAGE_SIZE,
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DMA_31BIT_MASK);
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if (info->lut_handle == NULL) {
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DRM_ERROR("cannot allocate PCIE lut page!\n");
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return DRM_ERR(ENOMEM);
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}
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lut = info->lut_handle->vaddr;
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for (i = 0; i < sg->pages; i++) {
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info->dev->sg->busaddr[i] = pci_map_page(info->dev->pdev,
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sg->pagelist[i],
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0,
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PAGE_SIZE,
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DMA_BIDIRECTIONAL);
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if (dma_mapping_error(info->dev->sg->busaddr[i])) {
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DRM_ERROR("cannot map GART backing store for DMA!\n");
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return DRM_ERR(-(info->dev->sg->busaddr[i]));
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}
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lut[i] = info->dev->sg->busaddr[i];
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}
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#if defined(__i386__) || defined(__x86_64__)
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asm volatile ("wbinvd":::"memory");
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#else
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mb();
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#endif
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/* Set GART in SFB */
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temp = DRM_READ8(info->mmio_map, 0xB00C);
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DRM_WRITE8(info->mmio_map, 0xB00C, temp & ~0x02);
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/* Set GART base address to HW */
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dwWriteReg(info->mmio_map, 0xB034, info->lut_handle->busaddr);
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return 0;
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}
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void xgi_pcie_lut_cleanup(struct xgi_info * info)
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{
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if (info->dev->sg) {
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drm_sg_free(info->dev, info->dev->sg->handle);
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}
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if (info->lut_handle) {
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drm_pci_free(info->dev, info->lut_handle);
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info->lut_handle = NULL;
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}
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}
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int xgi_pcie_heap_init(struct xgi_info * info)
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{
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int err;
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err = xgi_pcie_lut_init(info);
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if (err) {
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DRM_ERROR("xgi_pcie_lut_init failed\n");
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return err;
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}
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err = xgi_mem_heap_init(&info->pcie_heap, 0, info->pcie.size);
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if (err) {
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xgi_pcie_lut_cleanup(info);
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}
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return err;
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}
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int xgi_pcie_alloc(struct xgi_info * info, struct xgi_mem_alloc * alloc,
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DRMFILE filp)
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{
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struct xgi_mem_block *block;
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down(&info->pcie_sem);
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if ((alloc->owner == PCIE_3D) && (xgi_pcie_vertex_block)) {
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DRM_INFO("PCIE Vertex has been created, return directly.\n");
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block = xgi_pcie_vertex_block;
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}
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else if ((alloc->owner == PCIE_3D_CMDLIST) && (xgi_pcie_cmdlist_block)) {
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DRM_INFO("PCIE Cmdlist has been created, return directly.\n");
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block = xgi_pcie_cmdlist_block;
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}
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else if ((alloc->owner == PCIE_3D_SCRATCHPAD) && (xgi_pcie_scratchpad_block)) {
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DRM_INFO("PCIE Scratchpad has been created, return directly.\n");
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block = xgi_pcie_scratchpad_block;
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}
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else {
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block = xgi_mem_alloc(&info->pcie_heap, alloc->size, alloc->owner);
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if (alloc->owner == PCIE_3D) {
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xgi_pcie_vertex_block = block;
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}
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else if (alloc->owner == PCIE_3D_CMDLIST) {
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xgi_pcie_cmdlist_block = block;
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}
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else if (alloc->owner == PCIE_3D_SCRATCHPAD) {
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xgi_pcie_scratchpad_block = block;
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}
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}
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up(&info->pcie_sem);
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if (block == NULL) {
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alloc->location = XGI_MEMLOC_INVALID;
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alloc->size = 0;
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DRM_ERROR("PCIE RAM allocation failed\n");
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return DRM_ERR(ENOMEM);
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} else {
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DRM_INFO("PCIE RAM allocation succeeded: offset = 0x%lx\n",
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block->offset);
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alloc->location = XGI_MEMLOC_NON_LOCAL;
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alloc->size = block->size;
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alloc->hw_addr = block->offset + info->pcie.base;
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alloc->offset = block->offset;
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block->filp = filp;
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return 0;
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}
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}
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int xgi_pcie_alloc_ioctl(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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struct xgi_mem_alloc alloc;
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struct xgi_info *info = dev->dev_private;
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int err;
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DRM_COPY_FROM_USER_IOCTL(alloc, (struct xgi_mem_alloc __user *) data,
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sizeof(alloc));
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err = xgi_pcie_alloc(info, & alloc, filp);
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if (err) {
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return err;
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}
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DRM_COPY_TO_USER_IOCTL((struct xgi_mem_alloc __user *) data,
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alloc, sizeof(alloc));
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return 0;
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}
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/**
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* Free all blocks associated with a particular file handle.
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*/
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void xgi_pcie_free_all(struct xgi_info * info, DRMFILE filp)
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{
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if (!info->pcie_heap.initialized) {
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return;
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}
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down(&info->pcie_sem);
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do {
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struct xgi_mem_block *block;
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list_for_each_entry(block, &info->pcie_heap.used_list, list) {
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if (block->filp == filp) {
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break;
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}
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}
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if (&block->list == &info->pcie_heap.used_list) {
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break;
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}
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(void) xgi_pcie_free(info, block->offset, filp);
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} while(1);
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up(&info->pcie_sem);
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}
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int xgi_pcie_free(struct xgi_info * info, unsigned long offset, DRMFILE filp)
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{
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const bool isvertex = (xgi_pcie_vertex_block
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&& (xgi_pcie_vertex_block->offset == offset));
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int err;
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down(&info->pcie_sem);
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err = xgi_mem_free(&info->pcie_heap, offset, filp);
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up(&info->pcie_sem);
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if (err) {
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DRM_ERROR("xgi_pcie_free() failed at base 0x%lx\n", offset);
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}
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if (isvertex)
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xgi_pcie_vertex_block = NULL;
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return err;
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}
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int xgi_pcie_free_ioctl(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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struct xgi_info *info = dev->dev_private;
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u32 offset;
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DRM_COPY_FROM_USER_IOCTL(offset, (unsigned long __user *) data,
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sizeof(offset));
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return xgi_pcie_free(info, offset, filp);
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}
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/**
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* xgi_find_pcie_virt
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* @address: GE HW address
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*
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* Returns CPU virtual address. Assumes the CPU VAddr is continuous in not
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* the same block
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*/
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void *xgi_find_pcie_virt(struct xgi_info * info, u32 address)
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{
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const unsigned long offset = address - info->pcie.base;
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return ((u8 *) info->dev->sg->virtual) + offset;
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}
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/*
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address -- GE hw address
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*/
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int xgi_test_rwinkernel_ioctl(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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struct xgi_info *info = dev->dev_private;
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u32 address;
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u32 *virtaddr = 0;
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DRM_COPY_FROM_USER_IOCTL(address, (unsigned long __user *) data,
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sizeof(address));
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DRM_INFO("input GE HW addr is 0x%x\n", address);
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if (address == 0) {
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return DRM_ERR(EFAULT);
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}
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virtaddr = (u32 *)xgi_find_pcie_virt(info, address);
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DRM_INFO("convert to CPU virt addr 0x%p\n", virtaddr);
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if (virtaddr != NULL) {
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DRM_INFO("original [virtaddr] = 0x%x\n", *virtaddr);
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*virtaddr = 0x00f00fff;
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DRM_INFO("modified [virtaddr] = 0x%x\n", *virtaddr);
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} else {
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return DRM_ERR(EFAULT);
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}
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return 0;
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}
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