132 lines
3.9 KiB
C
132 lines
3.9 KiB
C
/****************************************************************************
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* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
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* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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***************************************************************************/
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#ifndef _XGI_DRM_H_
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#define _XGI_DRM_H_
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#include <linux/types.h>
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#include <asm/ioctl.h>
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struct drm_xgi_sarea {
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__u16 device_id;
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__u16 vendor_id;
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char device_name[32];
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unsigned int scrn_start;
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unsigned int scrn_xres;
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unsigned int scrn_yres;
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unsigned int scrn_bpp;
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unsigned int scrn_pitch;
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};
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struct xgi_bootstrap {
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/**
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* Size of PCI-e GART range in megabytes.
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*/
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struct drm_map gart;
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};
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enum xgi_mem_location {
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XGI_MEMLOC_NON_LOCAL = 0,
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XGI_MEMLOC_LOCAL = 1,
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XGI_MEMLOC_INVALID = 0x7fffffff
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};
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struct xgi_mem_alloc {
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unsigned int location;
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unsigned int size;
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unsigned int is_front;
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unsigned int owner;
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/**
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* Address of the memory from the graphics hardware's point of view.
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*/
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__u32 hw_addr;
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/**
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* Offset of the allocation in the mapping.
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*/
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__u32 offset;
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};
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enum xgi_batch_type {
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BTYPE_2D = 0,
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BTYPE_3D = 1,
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BTYPE_FLIP = 2,
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BTYPE_CTRL = 3,
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BTYPE_NONE = 0x7fffffff
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};
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struct xgi_cmd_info {
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__u32 type;
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__u32 hw_addr;
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__u32 size;
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__u32 id;
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};
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struct xgi_state_info {
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unsigned int _fromState;
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unsigned int _toState;
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};
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/*
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* Ioctl definitions
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*/
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#define DRM_XGI_BOOTSTRAP 0
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#define DRM_XGI_FB_ALLOC 1
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#define DRM_XGI_FB_FREE 2
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#define DRM_XGI_PCIE_ALLOC 3
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#define DRM_XGI_PCIE_FREE 4
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#define DRM_XGI_SUBMIT_CMDLIST 5
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#define DRM_XGI_GE_RESET 6
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#define DRM_XGI_DUMP_REGISTER 7
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#define DRM_XGI_DEBUG_INFO 8
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#define DRM_XGI_TEST_RWINKERNEL 9
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#define DRM_XGI_STATE_CHANGE 10
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#define XGI_IOCTL_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_BOOTSTRAP, struct xgi_bootstrap)
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#define XGI_IOCTL_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_FB_ALLOC, struct xgi_mem_alloc)
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#define XGI_IOCTL_FB_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_FB_FREE, __u32)
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#define XGI_IOCTL_PCIE_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_XGI_PCIE_ALLOC, struct xgi_mem_alloc)
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#define XGI_IOCTL_PCIE_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_PCIE_FREE, __u32)
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#define XGI_IOCTL_GE_RESET DRM_IO(DRM_COMMAND_BASE + DRM_XGI_GE_RESET)
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#define XGI_IOCTL_DUMP_REGISTER DRM_IO(DRM_COMMAND_BASE + DRM_XGI_DUMP_REGISTER)
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#define XGI_IOCTL_DEBUG_INFO DRM_IO(DRM_COMMAND_BASE + DRM_XGI_DEBUG_INFO)
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#define XGI_IOCTL_SUBMIT_CMDLIST DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_SUBMIT_CMDLIST, struct xgi_cmd_info)
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#define XGI_IOCTL_TEST_RWINKERNEL DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_TEST_RWINKERNEL, __u32)
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#define XGI_IOCTL_STATE_CHANGE DRM_IOW(DRM_COMMAND_BASE + DRM_XGI_STATE_CHANGE, struct xgi_state_info)
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#endif /* _XGI_DRM_H_ */
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