193 lines
4.8 KiB
C
193 lines
4.8 KiB
C
#ifndef _KGSL_DRM_H_
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#define _KGSL_DRM_H_
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#include "drm.h"
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#define DRM_KGSL_GEM_CREATE 0x00
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#define DRM_KGSL_GEM_PREP 0x01
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#define DRM_KGSL_GEM_SETMEMTYPE 0x02
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#define DRM_KGSL_GEM_GETMEMTYPE 0x03
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#define DRM_KGSL_GEM_MMAP 0x04
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#define DRM_KGSL_GEM_ALLOC 0x05
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#define DRM_KGSL_GEM_BIND_GPU 0x06
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#define DRM_KGSL_GEM_UNBIND_GPU 0x07
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#define DRM_KGSL_GEM_GET_BUFINFO 0x08
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#define DRM_KGSL_GEM_SET_BUFCOUNT 0x09
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#define DRM_KGSL_GEM_SET_ACTIVE 0x0A
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#define DRM_KGSL_GEM_LOCK_HANDLE 0x0B
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#define DRM_KGSL_GEM_UNLOCK_HANDLE 0x0C
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#define DRM_KGSL_GEM_UNLOCK_ON_TS 0x0D
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#define DRM_KGSL_GEM_CREATE_FD 0x0E
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#define DRM_IOCTL_KGSL_GEM_CREATE \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_CREATE, struct drm_kgsl_gem_create)
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#define DRM_IOCTL_KGSL_GEM_PREP \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_PREP, struct drm_kgsl_gem_prep)
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#define DRM_IOCTL_KGSL_GEM_SETMEMTYPE \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SETMEMTYPE, \
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struct drm_kgsl_gem_memtype)
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#define DRM_IOCTL_KGSL_GEM_GETMEMTYPE \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GETMEMTYPE, \
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struct drm_kgsl_gem_memtype)
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#define DRM_IOCTL_KGSL_GEM_MMAP \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_MMAP, struct drm_kgsl_gem_mmap)
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#define DRM_IOCTL_KGSL_GEM_ALLOC \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_ALLOC, struct drm_kgsl_gem_alloc)
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#define DRM_IOCTL_KGSL_GEM_BIND_GPU \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_BIND_GPU, struct drm_kgsl_gem_bind_gpu)
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#define DRM_IOCTL_KGSL_GEM_UNBIND_GPU \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNBIND_GPU, \
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struct drm_kgsl_gem_bind_gpu)
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#define DRM_IOCTL_KGSL_GEM_GET_BUFINFO \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_GET_BUFINFO, \
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struct drm_kgsl_gem_bufinfo)
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#define DRM_IOCTL_KGSL_GEM_SET_BUFCOUNT \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SET_BUFCOUNT, \
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struct drm_kgsl_gem_bufcount)
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#define DRM_IOCTL_KGSL_GEM_SET_ACTIVE \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_SET_ACTIVE, \
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struct drm_kgsl_gem_active)
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#define DRM_IOCTL_KGSL_GEM_LOCK_HANDLE \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_LOCK_HANDLE, \
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struct drm_kgsl_gem_lock_handles)
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#define DRM_IOCTL_KGSL_GEM_UNLOCK_HANDLE \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNLOCK_HANDLE, \
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struct drm_kgsl_gem_unlock_handles)
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#define DRM_IOCTL_KGSL_GEM_UNLOCK_ON_TS \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_UNLOCK_ON_TS, \
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struct drm_kgsl_gem_unlock_on_ts)
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#define DRM_IOCTL_KGSL_GEM_CREATE_FD \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_KGSL_GEM_CREATE_FD, \
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struct drm_kgsl_gem_create_fd)
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/* Maximum number of sub buffers per GEM object */
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#define DRM_KGSL_GEM_MAX_BUFFERS 2
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/* Memory types - these define the source and caching policies
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of the GEM memory chunk */
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/* Legacy definitions left for compatability */
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#define DRM_KGSL_GEM_TYPE_EBI 0
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#define DRM_KGSL_GEM_TYPE_SMI 1
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#define DRM_KGSL_GEM_TYPE_KMEM 2
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#define DRM_KGSL_GEM_TYPE_KMEM_NOCACHE 3
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#define DRM_KGSL_GEM_TYPE_MEM_MASK 0xF
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/* Contiguous memory (PMEM) */
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#define DRM_KGSL_GEM_TYPE_PMEM 0x000100
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/* PMEM memory types */
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#define DRM_KGSL_GEM_PMEM_EBI 0x001000
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#define DRM_KGSL_GEM_PMEM_SMI 0x002000
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/* Standard paged memory */
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#define DRM_KGSL_GEM_TYPE_MEM 0x010000
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/* Caching controls */
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#define DRM_KGSL_GEM_CACHE_NONE 0x000000
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#define DRM_KGSL_GEM_CACHE_WCOMBINE 0x100000
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#define DRM_KGSL_GEM_CACHE_WTHROUGH 0x200000
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#define DRM_KGSL_GEM_CACHE_WBACK 0x400000
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#define DRM_KGSL_GEM_CACHE_WBACKWA 0x800000
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#define DRM_KGSL_GEM_CACHE_MASK 0xF00000
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/* FD based objects */
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#define DRM_KGSL_GEM_TYPE_FD_FBMEM 0x1000000
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#define DRM_KGSL_GEM_TYPE_FD_MASK 0xF000000
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/* Timestamp types */
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#define DRM_KGSL_GEM_TS_3D 0x00000430
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#define DRM_KGSL_GEM_TS_2D 0x00000180
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struct drm_kgsl_gem_create {
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uint32_t size;
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uint32_t handle;
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};
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struct drm_kgsl_gem_prep {
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uint32_t handle;
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uint32_t phys;
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uint64_t offset;
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};
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struct drm_kgsl_gem_memtype {
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uint32_t handle;
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uint32_t type;
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};
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struct drm_kgsl_gem_mmap {
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uint32_t handle;
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uint32_t size;
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uint32_t hostptr;
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uint64_t offset;
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};
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struct drm_kgsl_gem_alloc {
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uint32_t handle;
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uint64_t offset;
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};
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struct drm_kgsl_gem_bind_gpu {
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uint32_t handle;
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uint32_t gpuptr;
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};
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struct drm_kgsl_gem_bufinfo {
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uint32_t handle;
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uint32_t count;
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uint32_t active;
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uint32_t offset[DRM_KGSL_GEM_MAX_BUFFERS];
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uint32_t gpuaddr[DRM_KGSL_GEM_MAX_BUFFERS];
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};
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struct drm_kgsl_gem_bufcount {
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uint32_t handle;
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uint32_t bufcount;
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};
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struct drm_kgsl_gem_active {
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uint32_t handle;
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uint32_t active;
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};
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struct drm_kgsl_gem_lock_handles {
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uint32_t num_handles;
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uint32_t *handle_list;
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uint32_t pid;
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uint32_t lock_id; /* Returned lock id used for unlocking */
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};
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struct drm_kgsl_gem_unlock_handles {
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uint32_t lock_id;
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};
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struct drm_kgsl_gem_unlock_on_ts {
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uint32_t lock_id;
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uint32_t timestamp; /* This field is a hw generated ts */
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uint32_t type; /* Which pipe to check for ts generation */
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};
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struct drm_kgsl_gem_create_fd {
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uint32_t fd;
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uint32_t handle;
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};
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#endif
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