330 lines
9.3 KiB
C
330 lines
9.3 KiB
C
/*
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* Copyright (c) 2007 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
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* 2004 Sylvain Meyer
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*
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* GPL/BSD dual license
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "drm_sarea.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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/**
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* i915_probe_agp - get AGP bootup configuration
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* @pdev: PCI device
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* @aperture_size: returns AGP aperture configured size
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* @preallocated_size: returns size of BIOS preallocated AGP space
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*
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* Since Intel integrated graphics are UMA, the BIOS has to set aside
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* some RAM for the framebuffer at early boot. This code figures out
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* how much was set aside so we can use it for our own purposes.
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*/
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int i915_probe_agp(struct pci_dev *pdev, unsigned long *aperture_size,
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unsigned long *preallocated_size)
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{
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struct pci_dev *bridge_dev;
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u16 tmp = 0;
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unsigned long overhead;
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bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
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if (!bridge_dev) {
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DRM_ERROR("bridge device not found\n");
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return -1;
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}
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/* Get the fb aperture size and "stolen" memory amount. */
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pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
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pci_dev_put(bridge_dev);
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*aperture_size = 1024 * 1024;
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*preallocated_size = 1024 * 1024;
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switch (pdev->device) {
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case PCI_DEVICE_ID_INTEL_82830_CGC:
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case PCI_DEVICE_ID_INTEL_82845G_IG:
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case PCI_DEVICE_ID_INTEL_82855GM_IG:
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case PCI_DEVICE_ID_INTEL_82865_IG:
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if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
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*aperture_size *= 64;
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else
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*aperture_size *= 128;
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break;
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default:
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/* 9xx supports large sizes, just look at the length */
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*aperture_size = pci_resource_len(pdev, 2);
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break;
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}
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/*
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* Some of the preallocated space is taken by the GTT
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* and popup. GTT is 1K per MB of aperture size, and popup is 4K.
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*/
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overhead = (*aperture_size / 1024) + 4096;
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switch (tmp & INTEL_855_GMCH_GMS_MASK) {
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case INTEL_855_GMCH_GMS_STOLEN_1M:
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break; /* 1M already */
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case INTEL_855_GMCH_GMS_STOLEN_4M:
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*preallocated_size *= 4;
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break;
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case INTEL_855_GMCH_GMS_STOLEN_8M:
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*preallocated_size *= 8;
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break;
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case INTEL_855_GMCH_GMS_STOLEN_16M:
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*preallocated_size *= 16;
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break;
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case INTEL_855_GMCH_GMS_STOLEN_32M:
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*preallocated_size *= 32;
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break;
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case INTEL_915G_GMCH_GMS_STOLEN_48M:
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*preallocated_size *= 48;
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break;
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case INTEL_915G_GMCH_GMS_STOLEN_64M:
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*preallocated_size *= 64;
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break;
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case INTEL_855_GMCH_GMS_DISABLED:
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DRM_ERROR("video memory is disabled\n");
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return -1;
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default:
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DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
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tmp & INTEL_855_GMCH_GMS_MASK);
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return -1;
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}
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*preallocated_size -= overhead;
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return 0;
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}
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/**
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* i915_driver_load - setup chip and create an initial config
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* @dev: DRM device
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* @flags: startup flags
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*
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* The driver load routine has to do several things:
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* - drive output discovery via intel_modeset_init()
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* - initialize the memory manager
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* - allocate initial config memory
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* - setup the DRM framebuffer with the allocated memory
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*/
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int i915_driver_load(struct drm_device *dev, unsigned long flags)
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{
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struct drm_i915_private *dev_priv;
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unsigned long agp_size, prealloc_size;
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unsigned long sareapage;
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int size, ret;
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dev_priv = drm_alloc(sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
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if (dev_priv == NULL)
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return -ENOMEM;
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memset(dev_priv, 0, sizeof(struct drm_i915_private));
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dev->dev_private = (void *)dev_priv;
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// dev_priv->flags = flags;
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/* i915 has 4 more counters */
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dev->counters += 4;
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dev->types[6] = _DRM_STAT_IRQ;
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dev->types[7] = _DRM_STAT_PRIMARY;
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dev->types[8] = _DRM_STAT_SECONDARY;
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dev->types[9] = _DRM_STAT_DMA;
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if (IS_I9XX(dev)) {
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dev_priv->mmiobase = drm_get_resource_start(dev, 0);
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dev_priv->mmiolen = drm_get_resource_len(dev, 0);
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dev->mode_config.fb_base =
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drm_get_resource_start(dev, 2) & 0xff000000;
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} else if (drm_get_resource_start(dev, 1)) {
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dev_priv->mmiobase = drm_get_resource_start(dev, 1);
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dev_priv->mmiolen = drm_get_resource_len(dev, 1);
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dev->mode_config.fb_base =
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drm_get_resource_start(dev, 0) & 0xff000000;
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} else {
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DRM_ERROR("Unable to find MMIO registers\n");
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return -ENODEV;
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}
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DRM_DEBUG("fb_base: 0x%08lx\n", dev->mode_config.fb_base);
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ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
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_DRM_REGISTERS, _DRM_READ_ONLY|_DRM_DRIVER, &dev_priv->mmio_map);
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if (ret != 0) {
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DRM_ERROR("Cannot add mapping for MMIO registers\n");
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return ret;
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}
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/* prebuild the SAREA */
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sareapage = max(SAREA_MAX, PAGE_SIZE);
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ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
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&dev_priv->sarea);
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if (ret) {
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DRM_ERROR("SAREA setup failed\n");
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return ret;
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}
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init_waitqueue_head(&dev->lock.lock_queue);
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/* FIXME: assume sarea_priv is right after SAREA */
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dev_priv->sarea_priv = dev_priv->sarea->handle + sizeof(struct drm_sarea);
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/*
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* Initialize the memory manager for local and AGP space
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*/
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drm_bo_driver_init(dev);
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i915_probe_agp(dev->pdev, &agp_size, &prealloc_size);
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printk("setting up %ld bytes of VRAM space\n", prealloc_size);
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printk("setting up %ld bytes of TT space\n", (agp_size - prealloc_size));
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drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, prealloc_size >> PAGE_SHIFT);
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drm_bo_init_mm(dev, DRM_BO_MEM_TT, prealloc_size >> PAGE_SHIFT, (agp_size - prealloc_size) >> PAGE_SHIFT);
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I915_WRITE(LP_RING + RING_LEN, 0);
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I915_WRITE(LP_RING + RING_HEAD, 0);
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I915_WRITE(LP_RING + RING_TAIL, 0);
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size = PRIMARY_RINGBUFFER_SIZE;
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ret = drm_buffer_object_create(dev, size, drm_bo_type_kernel,
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DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
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DRM_BO_FLAG_MEM_VRAM |
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DRM_BO_FLAG_NO_EVICT |
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DRM_BO_HINT_DONT_FENCE, 0, 0x1, 0,
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&dev_priv->ring_buffer);
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if (ret < 0) {
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DRM_ERROR("Unable to allocate or pin ring buffer\n");
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return -EINVAL;
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}
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/* remap the buffer object properly */
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dev_priv->ring.Start = dev_priv->ring_buffer->offset;
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dev_priv->ring.End = dev_priv->ring.Start + size;
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dev_priv->ring.Size = size;
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dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
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/* FIXME: need wrapper with PCI mem checks */
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ret = drm_mem_reg_ioremap(dev, &dev_priv->ring_buffer->mem,
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(void **) &dev_priv->ring.virtual_start);
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if (ret)
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DRM_ERROR("error mapping ring buffer: %d\n", ret);
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DRM_DEBUG("ring start %08lX, %p, %08lX\n", dev_priv->ring.Start,
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dev_priv->ring.virtual_start, dev_priv->ring.Size);
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dev_priv->sarea_priv->pf_current_page = 0;
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memset((void *)(dev_priv->ring.virtual_start), 0, dev_priv->ring.Size);
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I915_WRITE(LP_RING + RING_START, dev_priv->ring.Start);
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I915_WRITE(LP_RING + RING_LEN,
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((dev_priv->ring.Size - 4096) & RING_NR_PAGES) |
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(RING_NO_REPORT | RING_VALID));
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/* We are using separate values as placeholders for mechanisms for
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* private backbuffer/depthbuffer usage.
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*/
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dev_priv->use_mi_batchbuffer_start = 0;
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/* Allow hardware batchbuffers unless told otherwise.
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*/
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dev_priv->allow_batchbuffer = 1;
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/* Program Hardware Status Page */
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if (!IS_G33(dev)) {
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dev_priv->status_page_dmah =
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drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
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if (!dev_priv->status_page_dmah) {
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dev->dev_private = (void *)dev_priv;
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i915_dma_cleanup(dev);
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DRM_ERROR("Can not allocate hardware status page\n");
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return -ENOMEM;
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}
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dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
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dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
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memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
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I915_WRITE(I915REG_HWS_PGA, dev_priv->dma_status_page);
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}
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DRM_DEBUG("Enabled hardware status page\n");
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intel_modeset_init(dev);
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drm_initial_config(dev, false);
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return 0;
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}
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int i915_driver_unload(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->ring.virtual_start) {
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drm_core_ioremapfree(&dev_priv->ring.map, dev);
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}
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if (dev_priv->status_page_dmah) {
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drm_pci_free(dev, dev_priv->status_page_dmah);
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dev_priv->status_page_dmah = NULL;
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dev_priv->hw_status_page = NULL;
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dev_priv->dma_status_page = 0;
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/* Need to rewrite hardware status page */
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I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
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}
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if (dev_priv->status_gfx_addr) {
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dev_priv->status_gfx_addr = 0;
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drm_core_ioremapfree(&dev_priv->hws_map, dev);
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I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
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}
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I915_WRITE(LP_RING + RING_LEN, 0);
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intel_modeset_cleanup(dev);
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drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
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dev_priv->ring.virtual_start);
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DRM_DEBUG("usage is %d\n", atomic_read(&dev_priv->ring_buffer->usage));
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mutex_lock(&dev->struct_mutex);
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drm_bo_usage_deref_locked(&dev_priv->ring_buffer);
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if (drm_bo_clean_mm(dev, DRM_BO_MEM_TT)) {
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DRM_ERROR("Memory manager type 3 not clean. "
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"Delaying takedown\n");
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}
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if (drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM)) {
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DRM_ERROR("Memory manager type 3 not clean. "
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"Delaying takedown\n");
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}
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mutex_unlock(&dev->struct_mutex);
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drm_bo_driver_finish(dev);
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DRM_DEBUG("%p, %p\n", dev_priv->mmio_map, dev_priv->sarea);
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drm_rmmap(dev, dev_priv->mmio_map);
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drm_rmmap(dev, dev_priv->sarea);
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drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
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dev->dev_private = NULL;
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return 0;
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}
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void i915_driver_lastclose(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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i915_do_cleanup_pageflip(dev);
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//i915_mem_takedown(&(dev_priv->agp_heap));
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i915_dma_cleanup(dev);
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}
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void i915_driver_preclose(struct drm_device *dev, struct drm_file *filp)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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//i915_mem_release(dev, filp, dev_priv->agp_heap);
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}
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