639 lines
17 KiB
C
639 lines
17 KiB
C
/* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
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* Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
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*
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* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Gareth Hughes <gareth@valinux.com>
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*/
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#ifndef __MGA_DRV_H__
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#define __MGA_DRV_H__
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#ifndef u8
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#define u8 u_int8_t
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#define u16 u_int16_t
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#define u32 u_int32_t
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#endif
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typedef struct drm_mga_primary_buffer {
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u8 *start;
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u8 *end;
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int size;
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u32 tail;
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int space;
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volatile long wrapped;
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volatile u32 *status;
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u32 last_flush;
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u32 last_wrap;
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u32 high_mark;
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spinlock_t list_lock;
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} drm_mga_primary_buffer_t;
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typedef struct drm_mga_freelist {
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struct drm_mga_freelist *next;
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struct drm_mga_freelist *prev;
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drm_mga_age_t age;
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drm_buf_t *buf;
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} drm_mga_freelist_t;
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typedef struct {
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drm_mga_freelist_t *list_entry;
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int discard;
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int dispatched;
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} drm_mga_buf_priv_t;
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typedef struct drm_mga_private {
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drm_mga_primary_buffer_t prim;
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drm_mga_sarea_t *sarea_priv;
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drm_mga_freelist_t *head;
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drm_mga_freelist_t *tail;
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unsigned int warp_pipe;
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unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
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int chipset;
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int usec_timeout;
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u32 clear_cmd;
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u32 maccess;
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unsigned int fb_cpp;
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unsigned int front_offset;
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unsigned int front_pitch;
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unsigned int back_offset;
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unsigned int back_pitch;
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unsigned int depth_cpp;
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unsigned int depth_offset;
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unsigned int depth_pitch;
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unsigned int texture_offset;
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unsigned int texture_size;
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drm_map_t *sarea;
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drm_map_t *fb;
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drm_map_t *mmio;
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drm_map_t *status;
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drm_map_t *warp;
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drm_map_t *primary;
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drm_map_t *buffers;
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drm_map_t *agp_textures;
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} drm_mga_private_t;
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/* mga_dma.c */
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extern int mga_dma_init( DRM_OS_IOCTL );
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extern int mga_dma_flush( DRM_OS_IOCTL );
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extern int mga_dma_reset( DRM_OS_IOCTL );
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extern int mga_dma_buffers( DRM_OS_IOCTL );
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extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
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extern int mga_do_dma_idle( drm_mga_private_t *dev_priv );
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extern int mga_do_dma_reset( drm_mga_private_t *dev_priv );
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extern int mga_do_engine_reset( drm_mga_private_t *dev_priv );
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extern int mga_do_cleanup_dma( drm_device_t *dev );
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extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
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extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
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extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
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extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );
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/* mga_state.c */
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extern int mga_dma_clear( DRM_OS_IOCTL );
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extern int mga_dma_swap( DRM_OS_IOCTL );
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extern int mga_dma_vertex( DRM_OS_IOCTL );
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extern int mga_dma_indices( DRM_OS_IOCTL );
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extern int mga_dma_iload( DRM_OS_IOCTL );
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extern int mga_dma_blit( DRM_OS_IOCTL );
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/* mga_warp.c */
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extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
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extern int mga_warp_init( drm_mga_private_t *dev_priv );
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#define mga_flush_write_combine() DRM_OS_READMEMORYBARRIER
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#define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
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#define MGA_ADDR( reg ) (MGA_BASE(reg) + reg)
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#define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg )
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#define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg )
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#ifdef __alpha__
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#define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
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#define MGA_WRITE( reg, val ) do { wmb(); MGA_DEREF( reg ) = val; } while (0)
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#define MGA_WRITE8( reg, val ) do { wmb(); MGA_DEREF8( reg ) = val; } while (0)
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static inline u32 _MGA_READ(u32 *addr)
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{
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mb();
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return *(volatile u32 *)addr;
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}
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#else
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#define MGA_READ( reg ) MGA_DEREF( reg )
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#define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0)
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#define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0)
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#endif
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#define DWGREG0 0x1c00
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#define DWGREG0_END 0x1dff
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#define DWGREG1 0x2c00
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#define DWGREG1_END 0x2dff
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#define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
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#define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
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#define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
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#define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
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/* ================================================================
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* Helper macross...
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*/
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#define MGA_EMIT_STATE( dev_priv, dirty ) \
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do { \
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if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \
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if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \
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mga_g400_emit_state( dev_priv ); \
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} else { \
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mga_g200_emit_state( dev_priv ); \
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} \
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} \
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} while (0)
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#define LOCK_TEST_WITH_RETURN( dev ) \
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do { \
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if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
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dev->lock.pid != DRM_OS_CURRENTPID ) { \
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DRM_ERROR( "%s called without lock held\n", \
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__FUNCTION__ ); \
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DRM_OS_RETURN( EINVAL ); \
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} \
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} while (0)
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#define WRAP_TEST_WITH_RETURN( dev_priv ) \
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do { \
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if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
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if ( mga_is_idle( dev_priv ) ) { \
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mga_do_dma_wrap_end( dev_priv ); \
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} else if ( dev_priv->prim.space < \
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dev_priv->prim.high_mark ) { \
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if ( MGA_DMA_DEBUG ) \
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DRM_INFO( __FUNCTION__": wrap...\n" ); \
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DRM_OS_RETURN( EBUSY); \
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} \
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} \
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} while (0)
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#define WRAP_WAIT_WITH_RETURN( dev_priv ) \
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do { \
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if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
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if ( mga_do_wait_for_idle( dev_priv ) ) { \
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if ( MGA_DMA_DEBUG ) \
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DRM_INFO( __FUNCTION__": wrap...\n" ); \
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DRM_OS_RETURN( EBUSY); \
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} \
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mga_do_dma_wrap_end( dev_priv ); \
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} \
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} while (0)
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/* ================================================================
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* Primary DMA command stream
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*/
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#define MGA_VERBOSE 0
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#define DMA_LOCALS unsigned int write; volatile u8 *prim;
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#define DMA_BLOCK_SIZE (5 * sizeof(u32))
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#define BEGIN_DMA( n ) \
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do { \
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if ( MGA_VERBOSE ) { \
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DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \
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(n), __FUNCTION__ ); \
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DRM_INFO( " space=0x%x req=0x%x\n", \
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dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
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} \
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prim = dev_priv->prim.start; \
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write = dev_priv->prim.tail; \
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} while (0)
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#define BEGIN_DMA_WRAP() \
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do { \
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if ( MGA_VERBOSE ) { \
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DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \
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DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \
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} \
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prim = dev_priv->prim.start; \
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write = dev_priv->prim.tail; \
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} while (0)
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#define ADVANCE_DMA() \
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do { \
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dev_priv->prim.tail = write; \
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if ( MGA_VERBOSE ) { \
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DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
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write, dev_priv->prim.space ); \
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} \
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} while (0)
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#define FLUSH_DMA() \
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do { \
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if ( 0 ) { \
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DRM_INFO( __FUNCTION__ ":\n" ); \
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DRM_INFO( " tail=0x%06x head=0x%06lx\n", \
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dev_priv->prim.tail, \
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MGA_READ( MGA_PRIMADDRESS ) - \
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dev_priv->primary->offset ); \
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} \
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if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \
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if ( dev_priv->prim.space < \
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dev_priv->prim.high_mark ) { \
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mga_do_dma_wrap_start( dev_priv ); \
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} else { \
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mga_do_dma_flush( dev_priv ); \
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} \
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} \
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} while (0)
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/* Never use this, always use DMA_BLOCK(...) for primary DMA output.
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*/
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#define DMA_WRITE( offset, val ) \
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do { \
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if ( MGA_VERBOSE ) { \
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DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04x\n", \
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(u32)(val), write + (offset) * sizeof(u32) ); \
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} \
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*(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
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} while (0)
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#define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \
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do { \
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DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
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(DMAREG( reg1 ) << 8) | \
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(DMAREG( reg2 ) << 16) | \
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(DMAREG( reg3 ) << 24)) ); \
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DMA_WRITE( 1, val0 ); \
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DMA_WRITE( 2, val1 ); \
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DMA_WRITE( 3, val2 ); \
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DMA_WRITE( 4, val3 ); \
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write += DMA_BLOCK_SIZE; \
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} while (0)
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/* Buffer aging via primary DMA stream head pointer.
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*/
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#define SET_AGE( age, h, w ) \
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do { \
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(age)->head = h; \
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(age)->wrap = w; \
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} while (0)
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#define TEST_AGE( age, h, w ) ( (age)->wrap < w || \
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( (age)->wrap == w && \
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(age)->head < h ) )
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#define AGE_BUFFER( buf_priv ) \
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do { \
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drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
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if ( (buf_priv)->dispatched ) { \
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entry->age.head = (dev_priv->prim.tail + \
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dev_priv->primary->offset); \
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entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
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} else { \
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entry->age.head = 0; \
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entry->age.wrap = 0; \
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} \
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} while (0)
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#define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
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MGA_DWGENGSTS | \
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MGA_ENDPRDMASTS)
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#define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
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MGA_ENDPRDMASTS)
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#define MGA_DMA_DEBUG 0
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/* A reduced set of the mga registers.
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*/
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#define MGA_CRTC_INDEX 0x1fd4
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#define MGA_ALPHACTRL 0x2c7c
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#define MGA_AR0 0x1c60
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#define MGA_AR1 0x1c64
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#define MGA_AR2 0x1c68
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#define MGA_AR3 0x1c6c
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#define MGA_AR4 0x1c70
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#define MGA_AR5 0x1c74
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#define MGA_AR6 0x1c78
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#define MGA_CXBNDRY 0x1c80
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#define MGA_CXLEFT 0x1ca0
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#define MGA_CXRIGHT 0x1ca4
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#define MGA_DMAPAD 0x1c54
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#define MGA_DSTORG 0x2cb8
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#define MGA_DWGCTL 0x1c00
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# define MGA_OPCOD_MASK (15 << 0)
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# define MGA_OPCOD_TRAP (4 << 0)
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# define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
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# define MGA_OPCOD_BITBLT (8 << 0)
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# define MGA_OPCOD_ILOAD (9 << 0)
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# define MGA_ATYPE_MASK (7 << 4)
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# define MGA_ATYPE_RPL (0 << 4)
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# define MGA_ATYPE_RSTR (1 << 4)
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# define MGA_ATYPE_ZI (3 << 4)
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# define MGA_ATYPE_BLK (4 << 4)
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# define MGA_ATYPE_I (7 << 4)
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# define MGA_LINEAR (1 << 7)
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# define MGA_ZMODE_MASK (7 << 8)
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# define MGA_ZMODE_NOZCMP (0 << 8)
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# define MGA_ZMODE_ZE (2 << 8)
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# define MGA_ZMODE_ZNE (3 << 8)
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# define MGA_ZMODE_ZLT (4 << 8)
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# define MGA_ZMODE_ZLTE (5 << 8)
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# define MGA_ZMODE_ZGT (6 << 8)
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# define MGA_ZMODE_ZGTE (7 << 8)
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# define MGA_SOLID (1 << 11)
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# define MGA_ARZERO (1 << 12)
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# define MGA_SGNZERO (1 << 13)
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# define MGA_SHIFTZERO (1 << 14)
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# define MGA_BOP_MASK (15 << 16)
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# define MGA_BOP_ZERO (0 << 16)
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# define MGA_BOP_DST (10 << 16)
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# define MGA_BOP_SRC (12 << 16)
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# define MGA_BOP_ONE (15 << 16)
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# define MGA_TRANS_SHIFT 20
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# define MGA_TRANS_MASK (15 << 20)
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# define MGA_BLTMOD_MASK (15 << 25)
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# define MGA_BLTMOD_BMONOLEF (0 << 25)
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# define MGA_BLTMOD_BMONOWF (4 << 25)
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# define MGA_BLTMOD_PLAN (1 << 25)
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# define MGA_BLTMOD_BFCOL (2 << 25)
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# define MGA_BLTMOD_BU32BGR (3 << 25)
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# define MGA_BLTMOD_BU32RGB (7 << 25)
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# define MGA_BLTMOD_BU24BGR (11 << 25)
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# define MGA_BLTMOD_BU24RGB (15 << 25)
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# define MGA_PATTERN (1 << 29)
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# define MGA_TRANSC (1 << 30)
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# define MGA_CLIPDIS (1 << 31)
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#define MGA_DWGSYNC 0x2c4c
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#define MGA_FCOL 0x1c24
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#define MGA_FIFOSTATUS 0x1e10
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#define MGA_FOGCOL 0x1cf4
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#define MGA_FXBNDRY 0x1c84
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#define MGA_FXLEFT 0x1ca8
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#define MGA_FXRIGHT 0x1cac
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#define MGA_ICLEAR 0x1e18
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# define MGA_SOFTRAPICLR (1 << 0)
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#define MGA_IEN 0x1e1c
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# define MGA_SOFTRAPIEN (1 << 0)
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#define MGA_LEN 0x1c5c
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#define MGA_MACCESS 0x1c04
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#define MGA_PITCH 0x1c8c
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#define MGA_PLNWT 0x1c1c
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#define MGA_PRIMADDRESS 0x1e58
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# define MGA_DMA_GENERAL (0 << 0)
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# define MGA_DMA_BLIT (1 << 0)
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# define MGA_DMA_VECTOR (2 << 0)
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# define MGA_DMA_VERTEX (3 << 0)
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#define MGA_PRIMEND 0x1e5c
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# define MGA_PRIMNOSTART (1 << 0)
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# define MGA_PAGPXFER (1 << 1)
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#define MGA_PRIMPTR 0x1e50
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# define MGA_PRIMPTREN0 (1 << 0)
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# define MGA_PRIMPTREN1 (1 << 1)
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#define MGA_RST 0x1e40
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# define MGA_SOFTRESET (1 << 0)
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# define MGA_SOFTEXTRST (1 << 1)
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#define MGA_SECADDRESS 0x2c40
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#define MGA_SECEND 0x2c44
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#define MGA_SETUPADDRESS 0x2cd0
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#define MGA_SETUPEND 0x2cd4
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#define MGA_SGN 0x1c58
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#define MGA_SOFTRAP 0x2c48
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#define MGA_SRCORG 0x2cb4
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# define MGA_SRMMAP_MASK (1 << 0)
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# define MGA_SRCMAP_FB (0 << 0)
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# define MGA_SRCMAP_SYSMEM (1 << 0)
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# define MGA_SRCACC_MASK (1 << 1)
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# define MGA_SRCACC_PCI (0 << 1)
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# define MGA_SRCACC_AGP (1 << 1)
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#define MGA_STATUS 0x1e14
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# define MGA_SOFTRAPEN (1 << 0)
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# define MGA_DWGENGSTS (1 << 16)
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# define MGA_ENDPRDMASTS (1 << 17)
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#define MGA_STENCIL 0x2cc8
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#define MGA_STENCILCTL 0x2ccc
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#define MGA_TDUALSTAGE0 0x2cf8
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#define MGA_TDUALSTAGE1 0x2cfc
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#define MGA_TEXBORDERCOL 0x2c5c
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#define MGA_TEXCTL 0x2c30
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#define MGA_TEXCTL2 0x2c3c
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# define MGA_DUALTEX (1 << 7)
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# define MGA_G400_TC2_MAGIC (1 << 15)
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# define MGA_MAP1_ENABLE (1 << 31)
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#define MGA_TEXFILTER 0x2c58
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#define MGA_TEXHEIGHT 0x2c2c
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#define MGA_TEXORG 0x2c24
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# define MGA_TEXORGMAP_MASK (1 << 0)
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# define MGA_TEXORGMAP_FB (0 << 0)
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# define MGA_TEXORGMAP_SYSMEM (1 << 0)
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# define MGA_TEXORGACC_MASK (1 << 1)
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# define MGA_TEXORGACC_PCI (0 << 1)
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# define MGA_TEXORGACC_AGP (1 << 1)
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#define MGA_TEXORG1 0x2ca4
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#define MGA_TEXORG2 0x2ca8
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#define MGA_TEXORG3 0x2cac
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#define MGA_TEXORG4 0x2cb0
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#define MGA_TEXTRANS 0x2c34
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#define MGA_TEXTRANSHIGH 0x2c38
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#define MGA_TEXWIDTH 0x2c28
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#define MGA_WACCEPTSEQ 0x1dd4
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#define MGA_WCODEADDR 0x1e6c
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#define MGA_WFLAG 0x1dc4
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#define MGA_WFLAG1 0x1de0
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#define MGA_WFLAGNB 0x1e64
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#define MGA_WFLAGNB1 0x1e08
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#define MGA_WGETMSB 0x1dc8
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#define MGA_WIADDR 0x1dc0
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#define MGA_WIADDR2 0x1dd8
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# define MGA_WMODE_SUSPEND (0 << 0)
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# define MGA_WMODE_RESUME (1 << 0)
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# define MGA_WMODE_JUMP (2 << 0)
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# define MGA_WMODE_START (3 << 0)
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# define MGA_WAGP_ENABLE (1 << 2)
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#define MGA_WMISC 0x1e70
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# define MGA_WUCODECACHE_ENABLE (1 << 0)
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# define MGA_WMASTER_ENABLE (1 << 1)
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# define MGA_WCACHEFLUSH_ENABLE (1 << 3)
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#define MGA_WVRTXSZ 0x1dcc
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#define MGA_YBOT 0x1c9c
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#define MGA_YDST 0x1c90
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#define MGA_YDSTLEN 0x1c88
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#define MGA_YDSTORG 0x1c94
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#define MGA_YTOP 0x1c98
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#define MGA_ZORG 0x1c0c
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/* This finishes the current batch of commands
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*/
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#define MGA_EXEC 0x0100
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/* Warp registers
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*/
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#define MGA_WR0 0x2d00
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#define MGA_WR1 0x2d04
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#define MGA_WR2 0x2d08
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#define MGA_WR3 0x2d0c
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#define MGA_WR4 0x2d10
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#define MGA_WR5 0x2d14
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#define MGA_WR6 0x2d18
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#define MGA_WR7 0x2d1c
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#define MGA_WR8 0x2d20
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#define MGA_WR9 0x2d24
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#define MGA_WR10 0x2d28
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#define MGA_WR11 0x2d2c
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#define MGA_WR12 0x2d30
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#define MGA_WR13 0x2d34
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#define MGA_WR14 0x2d38
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#define MGA_WR15 0x2d3c
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#define MGA_WR16 0x2d40
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#define MGA_WR17 0x2d44
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#define MGA_WR18 0x2d48
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#define MGA_WR19 0x2d4c
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#define MGA_WR20 0x2d50
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#define MGA_WR21 0x2d54
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#define MGA_WR22 0x2d58
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#define MGA_WR23 0x2d5c
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#define MGA_WR24 0x2d60
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#define MGA_WR25 0x2d64
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#define MGA_WR26 0x2d68
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#define MGA_WR27 0x2d6c
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#define MGA_WR28 0x2d70
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#define MGA_WR29 0x2d74
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#define MGA_WR30 0x2d78
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#define MGA_WR31 0x2d7c
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#define MGA_WR32 0x2d80
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#define MGA_WR33 0x2d84
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#define MGA_WR34 0x2d88
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#define MGA_WR35 0x2d8c
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#define MGA_WR36 0x2d90
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#define MGA_WR37 0x2d94
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#define MGA_WR38 0x2d98
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#define MGA_WR39 0x2d9c
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#define MGA_WR40 0x2da0
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#define MGA_WR41 0x2da4
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#define MGA_WR42 0x2da8
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#define MGA_WR43 0x2dac
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#define MGA_WR44 0x2db0
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#define MGA_WR45 0x2db4
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#define MGA_WR46 0x2db8
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#define MGA_WR47 0x2dbc
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#define MGA_WR48 0x2dc0
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#define MGA_WR49 0x2dc4
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#define MGA_WR50 0x2dc8
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#define MGA_WR51 0x2dcc
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#define MGA_WR52 0x2dd0
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#define MGA_WR53 0x2dd4
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#define MGA_WR54 0x2dd8
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#define MGA_WR55 0x2ddc
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#define MGA_WR56 0x2de0
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#define MGA_WR57 0x2de4
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#define MGA_WR58 0x2de8
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#define MGA_WR59 0x2dec
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#define MGA_WR60 0x2df0
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#define MGA_WR61 0x2df4
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#define MGA_WR62 0x2df8
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#define MGA_WR63 0x2dfc
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# define MGA_G400_WR_MAGIC (1 << 6)
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# define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
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#define MGA_ILOAD_ALIGN 64
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#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
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#define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
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MGA_ATYPE_I | \
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MGA_ZMODE_NOZCMP | \
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MGA_ARZERO | \
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MGA_SGNZERO | \
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MGA_BOP_SRC | \
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(15 << MGA_TRANS_SHIFT))
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#define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
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MGA_ZMODE_NOZCMP | \
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MGA_SOLID | \
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MGA_ARZERO | \
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MGA_SGNZERO | \
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MGA_SHIFTZERO | \
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MGA_BOP_SRC | \
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(0 << MGA_TRANS_SHIFT) | \
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MGA_BLTMOD_BMONOLEF | \
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MGA_TRANSC | \
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MGA_CLIPDIS)
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|
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#define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
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MGA_ATYPE_RPL | \
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MGA_SGNZERO | \
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MGA_SHIFTZERO | \
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MGA_BOP_SRC | \
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(0 << MGA_TRANS_SHIFT) | \
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MGA_BLTMOD_BFCOL | \
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MGA_CLIPDIS)
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/* Simple idle test.
|
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*/
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static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv )
|
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{
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u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
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return ( status == MGA_ENDPRDMASTS );
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}
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#endif
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