553 lines
17 KiB
C
553 lines
17 KiB
C
/*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _I915_DRM_H_
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#define _I915_DRM_H_
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/* Please note that modifications to all structs defined here are
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* subject to backwards-compatibility constraints.
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*/
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#include "drm.h"
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/* Each region is a minimum of 16k, and there are at most 255 of them.
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*/
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#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
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* of chars for next/prev indices */
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#define I915_LOG_MIN_TEX_REGION_SIZE 14
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typedef struct _drm_i915_init {
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enum {
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I915_INIT_DMA = 0x01,
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I915_CLEANUP_DMA = 0x02,
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I915_RESUME_DMA = 0x03,
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/* Since this struct isn't versioned, just used a new
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* 'func' code to indicate the presence of dri2 sarea
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* info. */
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I915_INIT_DMA2 = 0x04
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} func;
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unsigned int mmio_offset;
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int sarea_priv_offset;
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unsigned int ring_start;
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unsigned int ring_end;
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unsigned int ring_size;
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unsigned int front_offset;
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unsigned int back_offset;
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unsigned int depth_offset;
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unsigned int w;
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unsigned int h;
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unsigned int pitch;
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unsigned int pitch_bits;
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unsigned int back_pitch;
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unsigned int depth_pitch;
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unsigned int cpp;
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unsigned int chipset;
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unsigned int sarea_handle;
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} drm_i915_init_t;
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typedef struct drm_i915_sarea {
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struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
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int last_upload; /* last time texture was uploaded */
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int last_enqueue; /* last time a buffer was enqueued */
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int last_dispatch; /* age of the most recently dispatched buffer */
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int ctxOwner; /* last context to upload state */
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int texAge;
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int pf_enabled; /* is pageflipping allowed? */
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int pf_active;
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int pf_current_page; /* which buffer is being displayed? */
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int perf_boxes; /* performance boxes to be displayed */
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int width, height; /* screen size in pixels */
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drm_handle_t front_handle;
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int front_offset;
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int front_size;
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drm_handle_t back_handle;
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int back_offset;
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int back_size;
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drm_handle_t depth_handle;
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int depth_offset;
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int depth_size;
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drm_handle_t tex_handle;
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int tex_offset;
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int tex_size;
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int log_tex_granularity;
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int pitch;
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int rotation; /* 0, 90, 180 or 270 */
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int rotated_offset;
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int rotated_size;
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int rotated_pitch;
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int virtualX, virtualY;
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unsigned int front_tiled;
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unsigned int back_tiled;
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unsigned int depth_tiled;
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unsigned int rotated_tiled;
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unsigned int rotated2_tiled;
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int planeA_x;
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int planeA_y;
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int planeA_w;
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int planeA_h;
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int planeB_x;
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int planeB_y;
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int planeB_w;
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int planeB_h;
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/* Triple buffering */
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drm_handle_t third_handle;
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int third_offset;
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int third_size;
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unsigned int third_tiled;
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/* buffer object handles for the static buffers. May change
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* over the lifetime of the client, though it doesn't in our current
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* implementation.
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*/
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unsigned int front_bo_handle;
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unsigned int back_bo_handle;
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unsigned int third_bo_handle;
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unsigned int depth_bo_handle;
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} drm_i915_sarea_t;
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/* Driver specific fence types and classes.
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*/
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/* The only fence class we support */
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#define DRM_I915_FENCE_CLASS_ACCEL 0
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/* Fence type that guarantees read-write flush */
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#define DRM_I915_FENCE_TYPE_RW 2
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/* MI_FLUSH programmed just before the fence */
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#define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
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/* Flags for perf_boxes
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*/
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#define I915_BOX_RING_EMPTY 0x1
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#define I915_BOX_FLIP 0x2
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#define I915_BOX_WAIT 0x4
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#define I915_BOX_TEXTURE_LOAD 0x8
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#define I915_BOX_LOST_CONTEXT 0x10
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/* I915 specific ioctls
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* The device specific ioctl range is 0x40 to 0x79.
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*/
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#define DRM_I915_INIT 0x00
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#define DRM_I915_FLUSH 0x01
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#define DRM_I915_FLIP 0x02
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#define DRM_I915_BATCHBUFFER 0x03
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#define DRM_I915_IRQ_EMIT 0x04
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#define DRM_I915_IRQ_WAIT 0x05
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#define DRM_I915_GETPARAM 0x06
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#define DRM_I915_SETPARAM 0x07
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#define DRM_I915_ALLOC 0x08
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#define DRM_I915_FREE 0x09
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#define DRM_I915_INIT_HEAP 0x0a
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#define DRM_I915_CMDBUFFER 0x0b
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#define DRM_I915_DESTROY_HEAP 0x0c
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#define DRM_I915_SET_VBLANK_PIPE 0x0d
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#define DRM_I915_GET_VBLANK_PIPE 0x0e
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#define DRM_I915_VBLANK_SWAP 0x0f
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#define DRM_I915_MMIO 0x10
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#define DRM_I915_HWS_ADDR 0x11
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#define DRM_I915_EXECBUFFER 0x12
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#define DRM_I915_GEM_INIT 0x13
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#define DRM_I915_GEM_EXECBUFFER 0x14
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#define DRM_I915_GEM_PIN 0x15
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#define DRM_I915_GEM_UNPIN 0x16
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#define DRM_I915_GEM_BUSY 0x17
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#define DRM_I915_GEM_THROTTLE 0x18
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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#define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
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#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
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#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
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#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
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#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
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#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
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#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
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#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
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#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
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#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
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#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
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#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
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#define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
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#define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
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#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
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#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
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#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
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#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
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#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
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/* Asynchronous page flipping:
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*/
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typedef struct drm_i915_flip {
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/*
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* This is really talking about planes, and we could rename it
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* except for the fact that some of the duplicated i915_drm.h files
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* out there check for HAVE_I915_FLIP and so might pick up this
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* version.
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*/
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int pipes;
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} drm_i915_flip_t;
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/* Allow drivers to submit batchbuffers directly to hardware, relying
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* on the security mechanisms provided by hardware.
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*/
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typedef struct drm_i915_batchbuffer {
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int start; /* agp offset */
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int used; /* nr bytes in use */
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int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
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int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
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int num_cliprects; /* mulitpass with multiple cliprects? */
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struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
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} drm_i915_batchbuffer_t;
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/* As above, but pass a pointer to userspace buffer which can be
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* validated by the kernel prior to sending to hardware.
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*/
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typedef struct _drm_i915_cmdbuffer {
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char __user *buf; /* pointer to userspace command buffer */
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int sz; /* nr bytes in buf */
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int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
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int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
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int num_cliprects; /* mulitpass with multiple cliprects? */
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struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
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} drm_i915_cmdbuffer_t;
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/* Userspace can request & wait on irq's:
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*/
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typedef struct drm_i915_irq_emit {
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int __user *irq_seq;
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} drm_i915_irq_emit_t;
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typedef struct drm_i915_irq_wait {
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int irq_seq;
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} drm_i915_irq_wait_t;
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/* Ioctl to query kernel params:
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*/
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#define I915_PARAM_IRQ_ACTIVE 1
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#define I915_PARAM_ALLOW_BATCHBUFFER 2
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#define I915_PARAM_LAST_DISPATCH 3
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#define I915_PARAM_CHIPSET_ID 4
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typedef struct drm_i915_getparam {
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int param;
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int __user *value;
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} drm_i915_getparam_t;
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/* Ioctl to set kernel params:
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*/
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#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
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#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
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#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
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typedef struct drm_i915_setparam {
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int param;
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int value;
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} drm_i915_setparam_t;
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/* A memory manager for regions of shared memory:
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*/
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#define I915_MEM_REGION_AGP 1
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typedef struct drm_i915_mem_alloc {
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int region;
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int alignment;
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int size;
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int __user *region_offset; /* offset from start of fb or agp */
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} drm_i915_mem_alloc_t;
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typedef struct drm_i915_mem_free {
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int region;
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int region_offset;
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} drm_i915_mem_free_t;
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typedef struct drm_i915_mem_init_heap {
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int region;
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int size;
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int start;
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} drm_i915_mem_init_heap_t;
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/* Allow memory manager to be torn down and re-initialized (eg on
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* rotate):
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*/
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typedef struct drm_i915_mem_destroy_heap {
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int region;
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} drm_i915_mem_destroy_heap_t;
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/* Allow X server to configure which pipes to monitor for vblank signals
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*/
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#define DRM_I915_VBLANK_PIPE_A 1
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#define DRM_I915_VBLANK_PIPE_B 2
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typedef struct drm_i915_vblank_pipe {
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int pipe;
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} drm_i915_vblank_pipe_t;
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/* Schedule buffer swap at given vertical blank:
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*/
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typedef struct drm_i915_vblank_swap {
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drm_drawable_t drawable;
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enum drm_vblank_seq_type seqtype;
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unsigned int sequence;
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} drm_i915_vblank_swap_t;
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#define I915_MMIO_READ 0
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#define I915_MMIO_WRITE 1
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#define I915_MMIO_MAY_READ 0x1
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#define I915_MMIO_MAY_WRITE 0x2
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#define MMIO_REGS_IA_PRIMATIVES_COUNT 0
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#define MMIO_REGS_IA_VERTICES_COUNT 1
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#define MMIO_REGS_VS_INVOCATION_COUNT 2
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#define MMIO_REGS_GS_PRIMITIVES_COUNT 3
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#define MMIO_REGS_GS_INVOCATION_COUNT 4
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#define MMIO_REGS_CL_PRIMITIVES_COUNT 5
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#define MMIO_REGS_CL_INVOCATION_COUNT 6
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#define MMIO_REGS_PS_INVOCATION_COUNT 7
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#define MMIO_REGS_PS_DEPTH_COUNT 8
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typedef struct drm_i915_mmio_entry {
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unsigned int flag;
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unsigned int offset;
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unsigned int size;
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} drm_i915_mmio_entry_t;
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typedef struct drm_i915_mmio {
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unsigned int read_write:1;
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unsigned int reg:31;
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void __user *data;
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} drm_i915_mmio_t;
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typedef struct drm_i915_hws_addr {
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uint64_t addr;
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} drm_i915_hws_addr_t;
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/*
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* Relocation header is 4 uint32_ts
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* 0 - 32 bit reloc count
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* 1 - 32-bit relocation type
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* 2-3 - 64-bit user buffer handle ptr for another list of relocs.
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*/
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#define I915_RELOC_HEADER 4
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/*
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* type 0 relocation has 4-uint32_t stride
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* 0 - offset into buffer
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* 1 - delta to add in
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* 2 - buffer handle
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* 3 - reserved (for optimisations later).
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*/
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/*
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* type 1 relocation has 4-uint32_t stride.
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* Hangs off the first item in the op list.
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* Performed after all valiations are done.
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* Try to group relocs into the same relocatee together for
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* performance reasons.
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* 0 - offset into buffer
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* 1 - delta to add in
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* 2 - buffer index in op list.
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* 3 - relocatee index in op list.
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*/
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#define I915_RELOC_TYPE_0 0
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#define I915_RELOC0_STRIDE 4
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#define I915_RELOC_TYPE_1 1
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#define I915_RELOC1_STRIDE 4
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struct drm_i915_op_arg {
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uint64_t next;
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uint64_t reloc_ptr;
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int handled;
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unsigned int pad64;
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union {
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struct drm_bo_op_req req;
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struct drm_bo_arg_rep rep;
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} d;
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};
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struct drm_i915_execbuffer {
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uint64_t ops_list;
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uint32_t num_buffers;
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struct drm_i915_batchbuffer batch;
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drm_context_t context; /* for lockless use in the future */
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struct drm_fence_arg fence_arg;
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};
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struct drm_i915_gem_init {
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/**
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* Beginning offset in the GTT to be managed by the DRM memory
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* manager.
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*/
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uint64_t gtt_start;
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/**
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* Ending offset in the GTT to be managed by the DRM memory
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* manager.
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*/
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uint64_t gtt_end;
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};
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struct drm_i915_gem_relocation_entry {
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/**
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* Handle of the buffer being pointed to by this relocation entry.
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*
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* It's appealing to make this be an index into the mm_validate_entry
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* list to refer to the buffer, but this allows the driver to create
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* a relocation list for state buffers and not re-write it per
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* exec using the buffer.
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*/
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uint32_t target_handle;
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/**
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* Value to be added to the offset of the target buffer to make up
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* the relocation entry.
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*/
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uint32_t delta;
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/** Offset in the buffer the relocation entry will be written into */
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uint64_t offset;
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/**
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* Offset value of the target buffer that the relocation entry was last
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* written as.
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*
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* If the buffer has the same offset as last time, we can skip syncing
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* and writing the relocation. This value is written back out by
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* the execbuffer ioctl when the relocation is written.
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*/
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uint64_t presumed_offset;
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/**
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* Target memory domains read by this operation.
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*/
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uint32_t read_domains;
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/**
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* Target memory domains written by this operation.
|
|
*
|
|
* Note that only one domain may be written by the whole
|
|
* execbuffer operation, so that where there are conflicts,
|
|
* the application will get -EINVAL back.
|
|
*/
|
|
uint32_t write_domain;
|
|
};
|
|
|
|
/**
|
|
* Intel memory domains
|
|
*
|
|
* Most of these just align with the various caches in
|
|
* the system and are used to flush and invalidate as
|
|
* objects end up cached in different domains.
|
|
*/
|
|
|
|
/* 0x00000001 is DRM_GEM_DOMAIN_CPU */
|
|
#define DRM_GEM_DOMAIN_I915_RENDER 0x00000002 /* Render cache, used by 2D and 3D drawing */
|
|
#define DRM_GEM_DOMAIN_I915_SAMPLER 0x00000004 /* Sampler cache, used by texture engine */
|
|
#define DRM_GEM_DOMAIN_I915_COMMAND 0x00000008 /* Command queue, used to load batch buffers */
|
|
#define DRM_GEM_DOMAIN_I915_INSTRUCTION 0x00000010 /* Instruction cache, used by shader programs */
|
|
#define DRM_GEM_DOMAIN_I915_VERTEX 0x00000020 /* Vertex address cache */
|
|
|
|
struct drm_i915_gem_exec_object {
|
|
/**
|
|
* User's handle for a buffer to be bound into the GTT for this
|
|
* operation.
|
|
*/
|
|
uint32_t handle;
|
|
|
|
/** List of relocations to be performed on this buffer */
|
|
uint32_t relocation_count;
|
|
uint64_t relocs_ptr; /* struct drm_i915_gem_relocation_entry *relocs */
|
|
|
|
/** Required alignment in graphics aperture */
|
|
uint64_t alignment;
|
|
|
|
/**
|
|
* Returned value of the updated offset of the object, for future
|
|
* presumed_offset writes.
|
|
*/
|
|
uint64_t offset;
|
|
};
|
|
|
|
struct drm_i915_gem_execbuffer {
|
|
/**
|
|
* List of buffers to be validated with their relocations to be
|
|
* performend on them.
|
|
*
|
|
* These buffers must be listed in an order such that all relocations
|
|
* a buffer is performing refer to buffers that have already appeared
|
|
* in the validate list.
|
|
*/
|
|
uint64_t buffers_ptr; /* struct drm_i915_gem_validate_entry *buffers */
|
|
uint32_t buffer_count;
|
|
|
|
/** Offset in the batchbuffer to start execution from. */
|
|
uint32_t batch_start_offset;
|
|
/** Bytes used in batchbuffer from batch_start_offset */
|
|
uint32_t batch_len;
|
|
uint32_t DR1;
|
|
uint32_t DR4;
|
|
uint32_t num_cliprects;
|
|
uint64_t cliprects_ptr; /* struct drm_clip_rect *cliprects */
|
|
};
|
|
|
|
struct drm_i915_gem_pin {
|
|
/** Handle of the buffer to be pinned. */
|
|
uint32_t handle;
|
|
uint32_t pad;
|
|
|
|
/** alignment required within the aperture */
|
|
uint64_t alignment;
|
|
|
|
/** Returned GTT offset of the buffer. */
|
|
uint64_t offset;
|
|
};
|
|
|
|
struct drm_i915_gem_unpin {
|
|
/** Handle of the buffer to be unpinned. */
|
|
uint32_t handle;
|
|
uint32_t pad;
|
|
};
|
|
|
|
struct drm_i915_gem_busy {
|
|
/** Handle of the buffer to check for busy */
|
|
uint32_t handle;
|
|
|
|
/** Return busy status (1 if busy, 0 if idle) */
|
|
uint32_t busy;
|
|
};
|
|
|
|
#endif /* _I915_DRM_H_ */
|