449 lines
13 KiB
C
449 lines
13 KiB
C
/*
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* Copyright (C) 2006 Ben Skeggs.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/*
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* Authors:
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* Ben Skeggs <darktama@iinet.net.au>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_reg.h"
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#include "nouveau_swmthd.h"
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void
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nouveau_irq_preinstall(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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/* Master disable */
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NV_WRITE(NV03_PMC_INTR_EN_0, 0);
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}
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void
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nouveau_irq_postinstall(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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/* Master enable */
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NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
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}
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void
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nouveau_irq_uninstall(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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/* Master disable */
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NV_WRITE(NV03_PMC_INTR_EN_0, 0);
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}
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static void
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nouveau_fifo_irq_handler(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t status;
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while ((status = NV_READ(NV03_PFIFO_INTR_0))) {
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uint32_t chid, get;
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NV_WRITE(NV03_PFIFO_CACHES, 0);
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chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
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(nouveau_fifo_number(dev) - 1);
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get = NV_READ(NV03_PFIFO_CACHE1_GET);
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if (status & NV_PFIFO_INTR_CACHE_ERROR) {
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uint32_t mthd, data;
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int ptr;
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ptr = get >> 2;
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if (dev_priv->card_type < NV_40) {
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mthd = NV_READ(NV04_PFIFO_CACHE1_METHOD(ptr));
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data = NV_READ(NV04_PFIFO_CACHE1_DATA(ptr));
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} else {
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mthd = NV_READ(NV40_PFIFO_CACHE1_METHOD(ptr));
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data = NV_READ(NV40_PFIFO_CACHE1_DATA(ptr));
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}
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DRM_INFO("PFIFO_CACHE_ERROR - "
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"Ch %d/%d Mthd 0x%04x Data 0x%08x\n",
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chid, (mthd >> 13) & 7, mthd & 0x1ffc, data);
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NV_WRITE(NV03_PFIFO_CACHE1_GET, get + 4);
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NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 1);
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status &= ~NV_PFIFO_INTR_CACHE_ERROR;
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NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
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}
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if (status & NV_PFIFO_INTR_DMA_PUSHER) {
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DRM_INFO("PFIFO_DMA_PUSHER - Ch %d\n", chid);
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status &= ~NV_PFIFO_INTR_DMA_PUSHER;
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NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);
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NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
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if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT) != get)
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NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, get + 4);
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}
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if (status) {
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DRM_INFO("Unhandled PFIFO_INTR - 0x%8x\n", status);
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NV_WRITE(NV03_PFIFO_INTR_0, status);
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}
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NV_WRITE(NV03_PFIFO_CACHES, 1);
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}
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NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
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}
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struct nouveau_bitfield_names {
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uint32_t mask;
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const char * name;
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};
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static struct nouveau_bitfield_names nouveau_nstatus_names[] =
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{
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{ NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
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{ NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
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{ NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
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{ NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }
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};
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static struct nouveau_bitfield_names nouveau_nstatus_names_nv10[] =
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{
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{ NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
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{ NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
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{ NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
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{ NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }
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};
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static struct nouveau_bitfield_names nouveau_nsource_names[] =
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{
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{ NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
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{ NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
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{ NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
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{ NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
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{ NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
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{ NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
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{ NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
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{ NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
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{ NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
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{ NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
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{ NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
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{ NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
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{ NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
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{ NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
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{ NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
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{ NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
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{ NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
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{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
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{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
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};
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static void
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nouveau_print_bitfield_names(uint32_t value,
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const struct nouveau_bitfield_names *namelist,
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const int namelist_len)
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{
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int i;
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for(i=0; i<namelist_len; ++i) {
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uint32_t mask = namelist[i].mask;
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if(value & mask) {
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printk(" %s", namelist[i].name);
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value &= ~mask;
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}
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}
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if(value)
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printk(" (unknown bits 0x%08x)", value);
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}
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static int
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nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int channel;
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if (dev_priv->card_type < NV_10) {
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channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
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} else if (dev_priv->card_type < NV_40) {
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channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
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} else
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if (dev_priv->card_type < NV_50) {
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uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 4;
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/* 0x400704 *sometimes* contains a sensible channel ID, but
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* mostly not.. for now lookup which channel owns the active
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* PGRAPH context. Probably a better way, but this'll do
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* for now.
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*/
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for (channel = 0; channel < 32; channel++) {
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if (dev_priv->fifos[channel] == NULL)
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continue;
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if (cur_grctx ==
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dev_priv->fifos[channel]->ramin_grctx->instance)
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break;
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}
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if (channel == 32) {
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DRM_ERROR("AIII, unable to determine active channel "
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"from PGRAPH context 0x%08x\n", cur_grctx);
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return -EINVAL;
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}
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} else {
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uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 12;
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for (channel = 0; channel < 128; channel++) {
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if (dev_priv->fifos[channel] == NULL)
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continue;
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if (cur_grctx ==
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dev_priv->fifos[channel]->ramin_grctx->instance)
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break;
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}
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if (channel == 128) {
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DRM_ERROR("AIII, unable to determine active channel "
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"from PGRAPH context 0x%08x\n", cur_grctx);
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return -EINVAL;
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}
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}
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if (channel > nouveau_fifo_number(dev) ||
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dev_priv->fifos[channel] == NULL) {
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DRM_ERROR("AIII, invalid/inactive channel id %d\n", channel);
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return -EINVAL;
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}
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*channel_ret = channel;
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return 0;
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}
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static void
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nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t address;
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uint32_t channel, class;
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uint32_t method, subc, data, data2;
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uint32_t nsource, nstatus;
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if (nouveau_graph_trapped_channel(dev, &channel))
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channel = -1;
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data = NV_READ(NV04_PGRAPH_TRAPPED_DATA);
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address = NV_READ(NV04_PGRAPH_TRAPPED_ADDR);
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method = address & 0x1FFC;
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if (dev_priv->card_type < NV_10) {
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subc = (address >> 13) & 0x7;
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data2= 0;
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} else {
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subc = (address >> 16) & 0x7;
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data2= NV_READ(NV10_PGRAPH_TRAPPED_DATA_HIGH);
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}
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nsource = NV_READ(NV03_PGRAPH_NSOURCE);
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nstatus = NV_READ(NV03_PGRAPH_NSTATUS);
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if (dev_priv->card_type < NV_10) {
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class = NV_READ(0x400180 + subc*4) & 0xFF;
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} else if (dev_priv->card_type < NV_40) {
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class = NV_READ(0x400160 + subc*4) & 0xFFF;
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} else if (dev_priv->card_type < NV_50) {
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class = NV_READ(0x400160 + subc*4) & 0xFFFF;
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} else {
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class = NV_READ(0x400814);
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}
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DRM_INFO("%s - nSource:", id);
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nouveau_print_bitfield_names(nsource, nouveau_nsource_names,
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ARRAY_SIZE(nouveau_nsource_names));
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printk(", nStatus:");
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if (dev_priv->card_type < NV_10)
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nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names,
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ARRAY_SIZE(nouveau_nstatus_names));
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else
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nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names_nv10,
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ARRAY_SIZE(nouveau_nstatus_names_nv10));
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printk("\n");
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DRM_INFO("%s - Ch %d/%d Class 0x%04x Mthd 0x%04x Data 0x%08x:0x%08x\n",
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id, channel, subc, class, method, data2, data);
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}
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static inline void
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nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int handled = 0;
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DRM_DEBUG("PGRAPH notify interrupt\n");
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if (dev_priv->card_type == NV_04 &&
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(nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
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uint32_t class, mthd;
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/* NV4 (nvidia TNT 1) reports software methods with
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* PGRAPH NOTIFY ILLEGAL_MTHD
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*/
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mthd = NV_READ(NV04_PGRAPH_TRAPPED_ADDR) & 0x1FFC;
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class = NV_READ(NV04_PGRAPH_CTX_SWITCH1) & 0xFFF;
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DRM_DEBUG("Got NV04 software method method %x for class %#x\n",
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mthd, class);
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if (nouveau_sw_method_execute(dev, class, mthd)) {
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DRM_ERROR("Unable to execute NV04 software method %x "
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"for object class %x. Please report.\n",
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mthd, class);
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} else {
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handled = 1;
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}
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}
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if (!handled)
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nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY");
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}
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static inline void
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nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
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{
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nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR");
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}
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static inline void
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nouveau_pgraph_intr_context_switch(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t chid;
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chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
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DRM_DEBUG("PGRAPH context switch interrupt channel %x\n", chid);
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switch(dev_priv->card_type) {
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case NV_04:
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case NV_05:
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nouveau_nv04_context_switch(dev);
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break;
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case NV_10:
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case NV_11:
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case NV_17:
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nouveau_nv10_context_switch(dev);
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break;
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default:
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DRM_ERROR("Context switch not implemented\n");
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break;
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}
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}
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static void
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nouveau_pgraph_irq_handler(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t status;
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while ((status = NV_READ(NV03_PGRAPH_INTR))) {
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uint32_t nsource = NV_READ(NV03_PGRAPH_NSOURCE);
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if (status & NV_PGRAPH_INTR_NOTIFY) {
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nouveau_pgraph_intr_notify(dev, nsource);
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status &= ~NV_PGRAPH_INTR_NOTIFY;
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NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
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}
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if (status & NV_PGRAPH_INTR_ERROR) {
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nouveau_pgraph_intr_error(dev, nsource);
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status &= ~NV_PGRAPH_INTR_ERROR;
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NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
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}
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if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
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nouveau_pgraph_intr_context_switch(dev);
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status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
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NV_WRITE(NV03_PGRAPH_INTR,
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NV_PGRAPH_INTR_CONTEXT_SWITCH);
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}
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if (status) {
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DRM_INFO("Unhandled PGRAPH_INTR - 0x%8x\n", status);
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NV_WRITE(NV03_PGRAPH_INTR, status);
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}
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if ((NV_READ(NV04_PGRAPH_FIFO) & (1 << 0)) == 0)
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NV_WRITE(NV04_PGRAPH_FIFO, 1);
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}
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NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
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}
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static void
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nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (crtc&1) {
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NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
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}
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if (crtc&2) {
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NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
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}
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}
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irqreturn_t
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nouveau_irq_handler(DRM_IRQ_ARGS)
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{
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struct drm_device *dev = (struct drm_device*)arg;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t status;
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status = NV_READ(NV03_PMC_INTR_0);
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if (!status)
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return IRQ_NONE;
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if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
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nouveau_fifo_irq_handler(dev);
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status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
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}
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if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
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nouveau_pgraph_irq_handler(dev);
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status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
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}
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if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
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nouveau_crtc_irq_handler(dev, (status>>24)&3);
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status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
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}
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if (status)
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DRM_ERROR("Unhandled PMC INTR status bits 0x%08x\n", status);
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return IRQ_HANDLED;
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}
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