911 lines
23 KiB
C
911 lines
23 KiB
C
/*
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* Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drm.h"
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#include "nouveau_drv.h"
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#define NV10_FIFO_NUMBER 32
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struct pipe_state {
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uint32_t pipe_0x0000[0x040/4];
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uint32_t pipe_0x0040[0x010/4];
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uint32_t pipe_0x0200[0x0c0/4];
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uint32_t pipe_0x4400[0x080/4];
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uint32_t pipe_0x6400[0x3b0/4];
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uint32_t pipe_0x6800[0x2f0/4];
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uint32_t pipe_0x6c00[0x030/4];
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uint32_t pipe_0x7000[0x130/4];
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uint32_t pipe_0x7400[0x0c0/4];
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uint32_t pipe_0x7800[0x0c0/4];
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};
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static int nv10_graph_ctx_regs [] = {
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NV10_PGRAPH_CTX_SWITCH1,
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NV10_PGRAPH_CTX_SWITCH2,
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NV10_PGRAPH_CTX_SWITCH3,
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NV10_PGRAPH_CTX_SWITCH4,
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NV10_PGRAPH_CTX_SWITCH5,
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NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */
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NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */
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NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */
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NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */
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NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */
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0x00400164,
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0x00400184,
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0x004001a4,
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0x004001c4,
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0x004001e4,
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0x00400168,
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0x00400188,
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0x004001a8,
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0x004001c8,
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0x004001e8,
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0x0040016c,
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0x0040018c,
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0x004001ac,
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0x004001cc,
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0x004001ec,
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0x00400170,
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0x00400190,
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0x004001b0,
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0x004001d0,
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0x004001f0,
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0x00400174,
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0x00400194,
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0x004001b4,
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0x004001d4,
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0x004001f4,
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0x00400178,
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0x00400198,
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0x004001b8,
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0x004001d8,
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0x004001f8,
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0x0040017c,
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0x0040019c,
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0x004001bc,
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0x004001dc,
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0x004001fc,
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NV10_PGRAPH_CTX_USER,
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NV04_PGRAPH_DMA_START_0,
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NV04_PGRAPH_DMA_START_1,
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NV04_PGRAPH_DMA_LENGTH,
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NV04_PGRAPH_DMA_MISC,
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NV10_PGRAPH_DMA_PITCH,
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NV04_PGRAPH_BOFFSET0,
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NV04_PGRAPH_BBASE0,
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NV04_PGRAPH_BLIMIT0,
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NV04_PGRAPH_BOFFSET1,
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NV04_PGRAPH_BBASE1,
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NV04_PGRAPH_BLIMIT1,
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NV04_PGRAPH_BOFFSET2,
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NV04_PGRAPH_BBASE2,
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NV04_PGRAPH_BLIMIT2,
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NV04_PGRAPH_BOFFSET3,
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NV04_PGRAPH_BBASE3,
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NV04_PGRAPH_BLIMIT3,
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NV04_PGRAPH_BOFFSET4,
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NV04_PGRAPH_BBASE4,
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NV04_PGRAPH_BLIMIT4,
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NV04_PGRAPH_BOFFSET5,
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NV04_PGRAPH_BBASE5,
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NV04_PGRAPH_BLIMIT5,
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NV04_PGRAPH_BPITCH0,
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NV04_PGRAPH_BPITCH1,
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NV04_PGRAPH_BPITCH2,
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NV04_PGRAPH_BPITCH3,
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NV04_PGRAPH_BPITCH4,
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NV10_PGRAPH_SURFACE,
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NV10_PGRAPH_STATE,
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NV04_PGRAPH_BSWIZZLE2,
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NV04_PGRAPH_BSWIZZLE5,
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NV04_PGRAPH_BPIXEL,
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NV10_PGRAPH_NOTIFY,
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NV04_PGRAPH_PATT_COLOR0,
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NV04_PGRAPH_PATT_COLOR1,
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NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
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0x00400904,
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0x00400908,
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0x0040090c,
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0x00400910,
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0x00400914,
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0x00400918,
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0x0040091c,
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0x00400920,
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0x00400924,
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0x00400928,
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0x0040092c,
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0x00400930,
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0x00400934,
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0x00400938,
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0x0040093c,
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0x00400940,
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0x00400944,
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0x00400948,
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0x0040094c,
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0x00400950,
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0x00400954,
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0x00400958,
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0x0040095c,
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0x00400960,
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0x00400964,
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0x00400968,
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0x0040096c,
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0x00400970,
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0x00400974,
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0x00400978,
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0x0040097c,
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0x00400980,
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0x00400984,
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0x00400988,
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0x0040098c,
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0x00400990,
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0x00400994,
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0x00400998,
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0x0040099c,
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0x004009a0,
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0x004009a4,
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0x004009a8,
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0x004009ac,
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0x004009b0,
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0x004009b4,
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0x004009b8,
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0x004009bc,
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0x004009c0,
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0x004009c4,
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0x004009c8,
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0x004009cc,
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0x004009d0,
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0x004009d4,
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0x004009d8,
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0x004009dc,
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0x004009e0,
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0x004009e4,
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0x004009e8,
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0x004009ec,
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0x004009f0,
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0x004009f4,
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0x004009f8,
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0x004009fc,
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NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */
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0x0040080c,
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NV04_PGRAPH_PATTERN_SHAPE,
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NV03_PGRAPH_MONO_COLOR0,
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NV04_PGRAPH_ROP3,
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NV04_PGRAPH_CHROMA,
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NV04_PGRAPH_BETA_AND,
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NV04_PGRAPH_BETA_PREMULT,
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0x00400e70,
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0x00400e74,
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0x00400e78,
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0x00400e7c,
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0x00400e80,
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0x00400e84,
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0x00400e88,
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0x00400e8c,
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0x00400ea0,
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0x00400ea4,
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0x00400ea8,
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0x00400e90,
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0x00400e94,
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0x00400e98,
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0x00400e9c,
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NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00 to 0x400f1c */
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NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */
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0x00400f04,
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0x00400f24,
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0x00400f08,
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0x00400f28,
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0x00400f0c,
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0x00400f2c,
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0x00400f10,
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0x00400f30,
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0x00400f14,
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0x00400f34,
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0x00400f18,
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0x00400f38,
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0x00400f1c,
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0x00400f3c,
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NV10_PGRAPH_XFMODE0,
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NV10_PGRAPH_XFMODE1,
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NV10_PGRAPH_GLOBALSTATE0,
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NV10_PGRAPH_GLOBALSTATE1,
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NV04_PGRAPH_STORED_FMT,
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NV04_PGRAPH_SOURCE_COLOR,
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NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */
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NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */
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0x00400404,
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0x00400484,
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0x00400408,
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0x00400488,
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0x0040040c,
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0x0040048c,
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0x00400410,
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0x00400490,
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0x00400414,
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0x00400494,
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0x00400418,
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0x00400498,
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0x0040041c,
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0x0040049c,
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0x00400420,
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0x004004a0,
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0x00400424,
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0x004004a4,
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0x00400428,
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0x004004a8,
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0x0040042c,
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0x004004ac,
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0x00400430,
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0x004004b0,
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0x00400434,
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0x004004b4,
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0x00400438,
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0x004004b8,
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0x0040043c,
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0x004004bc,
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0x00400440,
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0x004004c0,
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0x00400444,
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0x004004c4,
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0x00400448,
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0x004004c8,
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0x0040044c,
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0x004004cc,
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0x00400450,
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0x004004d0,
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0x00400454,
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0x004004d4,
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0x00400458,
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0x004004d8,
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0x0040045c,
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0x004004dc,
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0x00400460,
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0x004004e0,
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0x00400464,
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0x004004e4,
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0x00400468,
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0x004004e8,
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0x0040046c,
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0x004004ec,
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0x00400470,
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0x004004f0,
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0x00400474,
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0x004004f4,
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0x00400478,
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0x004004f8,
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0x0040047c,
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0x004004fc,
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NV03_PGRAPH_ABS_UCLIP_XMIN,
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NV03_PGRAPH_ABS_UCLIP_XMAX,
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NV03_PGRAPH_ABS_UCLIP_YMIN,
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NV03_PGRAPH_ABS_UCLIP_YMAX,
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0x00400550,
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0x00400558,
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0x00400554,
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0x0040055c,
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NV03_PGRAPH_ABS_UCLIPA_XMIN,
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NV03_PGRAPH_ABS_UCLIPA_XMAX,
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NV03_PGRAPH_ABS_UCLIPA_YMIN,
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NV03_PGRAPH_ABS_UCLIPA_YMAX,
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NV03_PGRAPH_ABS_ICLIP_XMAX,
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NV03_PGRAPH_ABS_ICLIP_YMAX,
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NV03_PGRAPH_XY_LOGIC_MISC0,
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NV03_PGRAPH_XY_LOGIC_MISC1,
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NV03_PGRAPH_XY_LOGIC_MISC2,
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NV03_PGRAPH_XY_LOGIC_MISC3,
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NV03_PGRAPH_CLIPX_0,
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NV03_PGRAPH_CLIPX_1,
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NV03_PGRAPH_CLIPY_0,
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NV03_PGRAPH_CLIPY_1,
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NV10_PGRAPH_COMBINER0_IN_ALPHA,
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NV10_PGRAPH_COMBINER1_IN_ALPHA,
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NV10_PGRAPH_COMBINER0_IN_RGB,
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NV10_PGRAPH_COMBINER1_IN_RGB,
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NV10_PGRAPH_COMBINER_COLOR0,
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NV10_PGRAPH_COMBINER_COLOR1,
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NV10_PGRAPH_COMBINER0_OUT_ALPHA,
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NV10_PGRAPH_COMBINER1_OUT_ALPHA,
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NV10_PGRAPH_COMBINER0_OUT_RGB,
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NV10_PGRAPH_COMBINER1_OUT_RGB,
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NV10_PGRAPH_COMBINER_FINAL0,
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NV10_PGRAPH_COMBINER_FINAL1,
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0x00400e00,
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0x00400e04,
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0x00400e08,
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0x00400e0c,
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0x00400e10,
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0x00400e14,
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0x00400e18,
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0x00400e1c,
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0x00400e20,
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0x00400e24,
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0x00400e28,
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0x00400e2c,
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0x00400e30,
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0x00400e34,
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0x00400e38,
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0x00400e3c,
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NV04_PGRAPH_PASSTHRU_0,
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NV04_PGRAPH_PASSTHRU_1,
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NV04_PGRAPH_PASSTHRU_2,
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NV10_PGRAPH_DIMX_TEXTURE,
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NV10_PGRAPH_WDIMX_TEXTURE,
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NV10_PGRAPH_DVD_COLORFMT,
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NV10_PGRAPH_SCALED_FORMAT,
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NV04_PGRAPH_MISC24_0,
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NV04_PGRAPH_MISC24_1,
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NV04_PGRAPH_MISC24_2,
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NV03_PGRAPH_X_MISC,
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NV03_PGRAPH_Y_MISC,
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NV04_PGRAPH_VALID1,
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NV04_PGRAPH_VALID2,
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};
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static int nv17_graph_ctx_regs [] = {
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NV10_PGRAPH_DEBUG_4,
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0x004006b0,
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0x00400eac,
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0x00400eb0,
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0x00400eb4,
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0x00400eb8,
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0x00400ebc,
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0x00400ec0,
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0x00400ec4,
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0x00400ec8,
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0x00400ecc,
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0x00400ed0,
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0x00400ed4,
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0x00400ed8,
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0x00400edc,
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0x00400ee0,
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0x00400a00,
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0x00400a04,
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};
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struct graph_state {
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int nv10[sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0])];
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int nv17[sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0])];
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struct pipe_state pipe_state;
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};
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static void nv10_graph_save_pipe(struct nouveau_channel *chan) {
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct graph_state* pgraph_ctx = chan->pgraph_ctx;
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struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state;
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int i;
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#define PIPE_SAVE(addr) \
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do { \
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NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \
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for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \
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fifo_pipe_state->pipe_##addr[i] = NV_READ(NV10_PGRAPH_PIPE_DATA); \
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} while (0)
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PIPE_SAVE(0x4400);
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PIPE_SAVE(0x0200);
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PIPE_SAVE(0x6400);
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PIPE_SAVE(0x6800);
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PIPE_SAVE(0x6c00);
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PIPE_SAVE(0x7000);
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PIPE_SAVE(0x7400);
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PIPE_SAVE(0x7800);
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PIPE_SAVE(0x0040);
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PIPE_SAVE(0x0000);
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#undef PIPE_SAVE
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}
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static void nv10_graph_load_pipe(struct nouveau_channel *chan) {
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct graph_state* pgraph_ctx = chan->pgraph_ctx;
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struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state;
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int i;
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uint32_t xfmode0, xfmode1;
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#define PIPE_RESTORE(addr) \
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do { \
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NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, addr); \
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for (i=0; i < sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]); i++) \
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NV_WRITE(NV10_PGRAPH_PIPE_DATA, fifo_pipe_state->pipe_##addr[i]); \
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} while (0)
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nouveau_wait_for_idle(dev);
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/* XXX check haiku comments */
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xfmode0 = NV_READ(NV10_PGRAPH_XFMODE0);
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xfmode1 = NV_READ(NV10_PGRAPH_XFMODE1);
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NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000);
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NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000);
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NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
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for (i = 0; i < 4; i++)
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NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
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for (i = 0; i < 4; i++)
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NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
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NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
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for (i = 0; i < 3; i++)
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NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
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NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
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for (i = 0; i < 3; i++)
|
|
NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
|
|
|
|
NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
|
|
NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008);
|
|
|
|
|
|
PIPE_RESTORE(0x0200);
|
|
nouveau_wait_for_idle(dev);
|
|
|
|
/* restore XFMODE */
|
|
NV_WRITE(NV10_PGRAPH_XFMODE0, xfmode0);
|
|
NV_WRITE(NV10_PGRAPH_XFMODE1, xfmode1);
|
|
PIPE_RESTORE(0x6400);
|
|
PIPE_RESTORE(0x6800);
|
|
PIPE_RESTORE(0x6c00);
|
|
PIPE_RESTORE(0x7000);
|
|
PIPE_RESTORE(0x7400);
|
|
PIPE_RESTORE(0x7800);
|
|
PIPE_RESTORE(0x4400);
|
|
PIPE_RESTORE(0x0000);
|
|
PIPE_RESTORE(0x0040);
|
|
nouveau_wait_for_idle(dev);
|
|
|
|
#undef PIPE_RESTORE
|
|
}
|
|
|
|
static void nv10_graph_create_pipe(struct nouveau_channel *chan) {
|
|
struct graph_state* pgraph_ctx = chan->pgraph_ctx;
|
|
struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state;
|
|
uint32_t *fifo_pipe_state_addr;
|
|
int i;
|
|
#define PIPE_INIT(addr) \
|
|
do { \
|
|
fifo_pipe_state_addr = fifo_pipe_state->pipe_##addr; \
|
|
} while (0)
|
|
#define PIPE_INIT_END(addr) \
|
|
do { \
|
|
if (fifo_pipe_state_addr != \
|
|
sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr) \
|
|
DRM_ERROR("incomplete pipe init for 0x%x : %p/%p\n", addr, fifo_pipe_state_addr, \
|
|
sizeof(fifo_pipe_state->pipe_##addr)/sizeof(fifo_pipe_state->pipe_##addr[0]) + fifo_pipe_state->pipe_##addr); \
|
|
} while (0)
|
|
#define NV_WRITE_PIPE_INIT(value) *(fifo_pipe_state_addr++) = value
|
|
|
|
PIPE_INIT(0x0200);
|
|
for (i = 0; i < 48; i++)
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
PIPE_INIT_END(0x0200);
|
|
|
|
PIPE_INIT(0x6400);
|
|
for (i = 0; i < 211; i++)
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x3f800000);
|
|
NV_WRITE_PIPE_INIT(0x40000000);
|
|
NV_WRITE_PIPE_INIT(0x40000000);
|
|
NV_WRITE_PIPE_INIT(0x40000000);
|
|
NV_WRITE_PIPE_INIT(0x40000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x3f800000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x3f000000);
|
|
NV_WRITE_PIPE_INIT(0x3f000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x3f800000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x3f800000);
|
|
NV_WRITE_PIPE_INIT(0x3f800000);
|
|
NV_WRITE_PIPE_INIT(0x3f800000);
|
|
NV_WRITE_PIPE_INIT(0x3f800000);
|
|
PIPE_INIT_END(0x6400);
|
|
|
|
PIPE_INIT(0x6800);
|
|
for (i = 0; i < 162; i++)
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x3f800000);
|
|
for (i = 0; i < 25; i++)
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
PIPE_INIT_END(0x6800);
|
|
|
|
PIPE_INIT(0x6c00);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0xbf800000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
PIPE_INIT_END(0x6c00);
|
|
|
|
PIPE_INIT(0x7000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x7149f2ca);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x7149f2ca);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x7149f2ca);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x7149f2ca);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x7149f2ca);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x7149f2ca);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x7149f2ca);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
NV_WRITE_PIPE_INIT(0x7149f2ca);
|
|
for (i = 0; i < 35; i++)
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
PIPE_INIT_END(0x7000);
|
|
|
|
PIPE_INIT(0x7400);
|
|
for (i = 0; i < 48; i++)
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
PIPE_INIT_END(0x7400);
|
|
|
|
PIPE_INIT(0x7800);
|
|
for (i = 0; i < 48; i++)
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
PIPE_INIT_END(0x7800);
|
|
|
|
PIPE_INIT(0x4400);
|
|
for (i = 0; i < 32; i++)
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
PIPE_INIT_END(0x4400);
|
|
|
|
PIPE_INIT(0x0000);
|
|
for (i = 0; i < 16; i++)
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
PIPE_INIT_END(0x0000);
|
|
|
|
PIPE_INIT(0x0040);
|
|
for (i = 0; i < 4; i++)
|
|
NV_WRITE_PIPE_INIT(0x00000000);
|
|
PIPE_INIT_END(0x0040);
|
|
|
|
#undef PIPE_INIT
|
|
#undef PIPE_INIT_END
|
|
#undef NV_WRITE_PIPE_INIT
|
|
}
|
|
|
|
static int nv10_graph_ctx_regs_find_offset(struct drm_device *dev, int reg)
|
|
{
|
|
int i;
|
|
for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) {
|
|
if (nv10_graph_ctx_regs[i] == reg)
|
|
return i;
|
|
}
|
|
DRM_ERROR("unknow offset nv10_ctx_regs %d\n", reg);
|
|
return -1;
|
|
}
|
|
|
|
static int nv17_graph_ctx_regs_find_offset(struct drm_device *dev, int reg)
|
|
{
|
|
int i;
|
|
for (i = 0; i < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++) {
|
|
if (nv17_graph_ctx_regs[i] == reg)
|
|
return i;
|
|
}
|
|
DRM_ERROR("unknow offset nv17_ctx_regs %d\n", reg);
|
|
return -1;
|
|
}
|
|
|
|
int nv10_graph_load_context(struct nouveau_channel *chan)
|
|
{
|
|
struct drm_device *dev = chan->dev;
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct graph_state* pgraph_ctx = chan->pgraph_ctx;
|
|
int i;
|
|
|
|
for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
|
|
NV_WRITE(nv10_graph_ctx_regs[i], pgraph_ctx->nv10[i]);
|
|
if (dev_priv->chipset>=0x17) {
|
|
for (i = 0; i < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++)
|
|
NV_WRITE(nv17_graph_ctx_regs[i], pgraph_ctx->nv17[i]);
|
|
}
|
|
|
|
nv10_graph_load_pipe(chan);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int nv10_graph_save_context(struct nouveau_channel *chan)
|
|
{
|
|
struct drm_device *dev = chan->dev;
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct graph_state* pgraph_ctx = chan->pgraph_ctx;
|
|
int i;
|
|
|
|
for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
|
|
pgraph_ctx->nv10[i] = NV_READ(nv10_graph_ctx_regs[i]);
|
|
if (dev_priv->chipset>=0x17) {
|
|
for (i = 0; i < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++)
|
|
pgraph_ctx->nv17[i] = NV_READ(nv17_graph_ctx_regs[i]);
|
|
}
|
|
|
|
nv10_graph_save_pipe(chan);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void nouveau_nv10_context_switch(struct drm_device *dev)
|
|
{
|
|
struct drm_nouveau_private *dev_priv;
|
|
struct nouveau_channel *next, *last;
|
|
int chid;
|
|
|
|
if (!dev) {
|
|
DRM_DEBUG("Invalid drm_device\n");
|
|
return;
|
|
}
|
|
dev_priv = dev->dev_private;
|
|
if (!dev_priv) {
|
|
DRM_DEBUG("Invalid drm_nouveau_private\n");
|
|
return;
|
|
}
|
|
if (!dev_priv->fifos) {
|
|
DRM_DEBUG("Invalid drm_nouveau_private->fifos\n");
|
|
return;
|
|
}
|
|
|
|
chid = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20)&(nouveau_fifo_number(dev)-1);
|
|
next = dev_priv->fifos[chid];
|
|
|
|
if (!next) {
|
|
DRM_ERROR("Invalid next channel\n");
|
|
return;
|
|
}
|
|
|
|
chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
|
|
last = dev_priv->fifos[chid];
|
|
|
|
if (!last) {
|
|
DRM_INFO("WARNING: Invalid last channel, switch to %x\n",
|
|
next->id);
|
|
} else {
|
|
DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",
|
|
last->id, next->id);
|
|
}
|
|
|
|
NV_WRITE(NV04_PGRAPH_FIFO,0x0);
|
|
if (last) {
|
|
nouveau_wait_for_idle(dev);
|
|
nv10_graph_save_context(last);
|
|
}
|
|
|
|
nouveau_wait_for_idle(dev);
|
|
|
|
NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000);
|
|
|
|
nouveau_wait_for_idle(dev);
|
|
|
|
nv10_graph_load_context(next);
|
|
|
|
NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
|
|
NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
|
|
NV_WRITE(NV04_PGRAPH_FIFO,0x1);
|
|
}
|
|
|
|
#define NV_WRITE_CTX(reg, val) do { \
|
|
int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \
|
|
if (offset > 0) \
|
|
pgraph_ctx->nv10[offset] = val; \
|
|
} while (0)
|
|
|
|
#define NV17_WRITE_CTX(reg, val) do { \
|
|
int offset = nv17_graph_ctx_regs_find_offset(dev, reg); \
|
|
if (offset > 0) \
|
|
pgraph_ctx->nv17[offset] = val; \
|
|
} while (0)
|
|
|
|
int nv10_graph_create_context(struct nouveau_channel *chan) {
|
|
struct drm_device *dev = chan->dev;
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct graph_state* pgraph_ctx;
|
|
|
|
DRM_DEBUG("nv10_graph_context_create %d\n", chan->id);
|
|
|
|
chan->pgraph_ctx = pgraph_ctx = drm_calloc(1, sizeof(*pgraph_ctx),
|
|
DRM_MEM_DRIVER);
|
|
|
|
if (pgraph_ctx == NULL)
|
|
return -ENOMEM;
|
|
|
|
/* mmio trace suggest that should be done in ddx with methods/objects */
|
|
#if 0
|
|
uint32_t tmp, vramsz;
|
|
/* per channel init from ddx */
|
|
tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
|
|
/*XXX the original ddx code, does this in 2 steps :
|
|
* tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
|
|
* NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
|
|
* tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
|
|
* NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
|
|
*/
|
|
tmp |= 0x00020100;
|
|
NV_WRITE_CTX(NV10_PGRAPH_SURFACE, tmp);
|
|
|
|
vramsz = drm_get_resource_len(dev, 0) - 1;
|
|
NV_WRITE_CTX(NV04_PGRAPH_BOFFSET0, 0);
|
|
NV_WRITE_CTX(NV04_PGRAPH_BOFFSET1, 0);
|
|
NV_WRITE_CTX(NV04_PGRAPH_BLIMIT0 , vramsz);
|
|
NV_WRITE_CTX(NV04_PGRAPH_BLIMIT1 , vramsz);
|
|
|
|
NV_WRITE_CTX(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
|
|
NV_WRITE_CTX(NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
|
|
|
|
NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
|
|
NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
|
|
NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
|
|
NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
|
|
#endif
|
|
|
|
NV_WRITE_CTX(0x00400e88, 0x08000000);
|
|
NV_WRITE_CTX(0x00400e9c, 0x4b7fffff);
|
|
NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff);
|
|
NV_WRITE_CTX(0x00400e10, 0x00001000);
|
|
NV_WRITE_CTX(0x00400e14, 0x00001000);
|
|
NV_WRITE_CTX(0x00400e30, 0x00080008);
|
|
NV_WRITE_CTX(0x00400e34, 0x00080008);
|
|
if (dev_priv->chipset>=0x17) {
|
|
/* is it really needed ??? */
|
|
NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4, NV_READ(NV10_PGRAPH_DEBUG_4));
|
|
NV17_WRITE_CTX(0x004006b0, NV_READ(0x004006b0));
|
|
NV17_WRITE_CTX(0x00400eac, 0x0fff0000);
|
|
NV17_WRITE_CTX(0x00400eb0, 0x0fff0000);
|
|
NV17_WRITE_CTX(0x00400ec0, 0x00000080);
|
|
NV17_WRITE_CTX(0x00400ed0, 0x00000080);
|
|
}
|
|
NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->id << 24);
|
|
|
|
nv10_graph_create_pipe(chan);
|
|
return 0;
|
|
}
|
|
|
|
void nv10_graph_destroy_context(struct nouveau_channel *chan)
|
|
{
|
|
struct drm_device *dev = chan->dev;
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct graph_state* pgraph_ctx = chan->pgraph_ctx;
|
|
int chid;
|
|
|
|
drm_free(pgraph_ctx, sizeof(*pgraph_ctx), DRM_MEM_DRIVER);
|
|
chan->pgraph_ctx = NULL;
|
|
|
|
chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
|
|
|
|
/* This code seems to corrupt the 3D pipe, but blob seems to do similar things ????
|
|
*/
|
|
#if 0
|
|
/* does this avoid a potential context switch while we are written graph
|
|
* reg, or we should mask graph interrupt ???
|
|
*/
|
|
NV_WRITE(NV04_PGRAPH_FIFO,0x0);
|
|
if (chid == chan->id) {
|
|
DRM_INFO("cleanning a channel with graph in current context\n");
|
|
nouveau_wait_for_idle(dev);
|
|
DRM_INFO("reseting current graph context\n");
|
|
/* can't be call here because of dynamic mem alloc */
|
|
//nv10_graph_create_context(chan);
|
|
nv10_graph_load_context(chan);
|
|
}
|
|
NV_WRITE(NV04_PGRAPH_FIFO, 0x1);
|
|
#else
|
|
if (chid == chan->id) {
|
|
DRM_INFO("cleanning a channel with graph in current context\n");
|
|
}
|
|
#endif
|
|
}
|
|
|
|
int nv10_graph_init(struct drm_device *dev) {
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
int i;
|
|
|
|
NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
|
|
~NV_PMC_ENABLE_PGRAPH);
|
|
NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
|
|
NV_PMC_ENABLE_PGRAPH);
|
|
|
|
NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);
|
|
NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
|
|
|
|
NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
|
|
NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
|
|
NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700);
|
|
//NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x24E00810); /* 0x25f92ad9 */
|
|
NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
|
|
NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x55DE0830 |
|
|
(1<<29) |
|
|
(1<<31));
|
|
if (dev_priv->chipset>=0x17) {
|
|
NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x1f000000);
|
|
NV_WRITE(0x004006b0, 0x40000020);
|
|
}
|
|
else
|
|
NV_WRITE(NV10_PGRAPH_DEBUG_4, 0x00000000);
|
|
|
|
/* copy tile info from PFB */
|
|
for (i=0; i<NV10_PFB_TILE__SIZE; i++) {
|
|
NV_WRITE(NV10_PGRAPH_TILE(i), NV_READ(NV10_PFB_TILE(i)));
|
|
NV_WRITE(NV10_PGRAPH_TLIMIT(i), NV_READ(NV10_PFB_TLIMIT(i)));
|
|
NV_WRITE(NV10_PGRAPH_TSIZE(i), NV_READ(NV10_PFB_TSIZE(i)));
|
|
NV_WRITE(NV10_PGRAPH_TSTATUS(i), NV_READ(NV10_PFB_TSTATUS(i)));
|
|
}
|
|
|
|
NV_WRITE(NV10_PGRAPH_CTX_SWITCH1, 0x00000000);
|
|
NV_WRITE(NV10_PGRAPH_CTX_SWITCH2, 0x00000000);
|
|
NV_WRITE(NV10_PGRAPH_CTX_SWITCH3, 0x00000000);
|
|
NV_WRITE(NV10_PGRAPH_CTX_SWITCH4, 0x00000000);
|
|
NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
|
|
NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF);
|
|
NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void nv10_graph_takedown(struct drm_device *dev)
|
|
{
|
|
}
|
|
|