365 lines
9.8 KiB
C
365 lines
9.8 KiB
C
/**
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* \file ati_pcigart.c
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* ATI PCI GART support
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*
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* \author Gareth Hughes <gareth@valinux.com>
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*/
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/*
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* Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
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*
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
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# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
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#define ATI_PCIE_WRITE 0x4
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#define ATI_PCIE_READ 0x8
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static __inline__ void gart_insert_page_into_table(struct drm_ati_pcigart_info *gart_info, dma_addr_t addr, volatile u32 *pci_gart)
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{
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u32 page_base;
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page_base = (u32)addr & ATI_PCIGART_PAGE_MASK;
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switch(gart_info->gart_reg_if) {
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case DRM_ATI_GART_IGP:
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page_base |= (upper_32_bits(addr) & 0xff) << 4;
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page_base |= 0xc;
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break;
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case DRM_ATI_GART_PCIE:
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page_base >>= 8;
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page_base |= (upper_32_bits(addr) & 0xff) << 24;
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page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE;
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break;
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default:
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case DRM_ATI_GART_PCI:
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break;
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}
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*pci_gart = cpu_to_le32(page_base);
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}
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static __inline__ dma_addr_t gart_get_page_from_table(struct drm_ati_pcigart_info *gart_info, volatile u32 *pci_gart)
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{
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dma_addr_t retval;
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switch(gart_info->gart_reg_if) {
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case DRM_ATI_GART_IGP:
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retval = (*pci_gart & ATI_PCIGART_PAGE_MASK);
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retval += (((*pci_gart & 0xf0) >> 4) << 16) << 16;
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break;
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case DRM_ATI_GART_PCIE:
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retval = (*pci_gart & ~0xc);
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retval <<= 8;
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break;
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case DRM_ATI_GART_PCI:
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retval = *pci_gart;
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break;
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}
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return retval;
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}
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int drm_ati_alloc_pcigart_table(struct drm_device *dev,
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struct drm_ati_pcigart_info *gart_info)
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{
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gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
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PAGE_SIZE,
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gart_info->table_mask);
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if (gart_info->table_handle == NULL)
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return -ENOMEM;
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#ifdef CONFIG_X86
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/* IGPs only exist on x86 in any case */
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if (gart_info->gart_reg_if == DRM_ATI_GART_IGP)
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set_memory_uc((unsigned long)gart_info->table_handle->vaddr, gart_info->table_size >> PAGE_SHIFT);
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#endif
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memset(gart_info->table_handle->vaddr, 0, gart_info->table_size);
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return 0;
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}
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EXPORT_SYMBOL(drm_ati_alloc_pcigart_table);
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static void drm_ati_free_pcigart_table(struct drm_device *dev,
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struct drm_ati_pcigart_info *gart_info)
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{
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#ifdef CONFIG_X86
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/* IGPs only exist on x86 in any case */
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if (gart_info->gart_reg_if == DRM_ATI_GART_IGP)
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set_memory_wb((unsigned long)gart_info->table_handle->vaddr, gart_info->table_size >> PAGE_SHIFT);
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#endif
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drm_pci_free(dev, gart_info->table_handle);
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gart_info->table_handle = NULL;
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}
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int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
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{
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struct drm_sg_mem *entry = dev->sg;
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unsigned long pages;
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int i;
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int max_pages;
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/* we need to support large memory configurations */
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if (!entry) {
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return 0;
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}
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if (gart_info->bus_addr) {
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max_pages = (gart_info->table_size / sizeof(u32));
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pages = (entry->pages <= max_pages)
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? entry->pages : max_pages;
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for (i = 0; i < pages; i++) {
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if (!entry->busaddr[i])
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break;
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pci_unmap_page(dev->pdev, entry->busaddr[i],
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PAGE_SIZE, PCI_DMA_TODEVICE);
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}
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if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
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gart_info->bus_addr = 0;
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}
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if (gart_info->gart_table_location == DRM_ATI_GART_MAIN
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&& gart_info->table_handle) {
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drm_ati_free_pcigart_table(dev, gart_info);
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}
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return 1;
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}
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EXPORT_SYMBOL(drm_ati_pcigart_cleanup);
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int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
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{
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struct drm_sg_mem *entry = dev->sg;
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void *address = NULL;
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unsigned long pages;
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u32 *pci_gart;
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dma_addr_t bus_address = 0;
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int i, j, ret = 0;
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int max_pages;
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dma_addr_t entry_addr;
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if (gart_info->gart_table_location == DRM_ATI_GART_MAIN && gart_info->table_handle == NULL) {
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DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
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ret = drm_ati_alloc_pcigart_table(dev, gart_info);
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if (ret) {
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DRM_ERROR("cannot allocate PCI GART page!\n");
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goto done;
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}
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}
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if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
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address = gart_info->table_handle->vaddr;
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bus_address = gart_info->table_handle->busaddr;
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} else {
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address = gart_info->addr;
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bus_address = gart_info->bus_addr;
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}
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if (!entry) {
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DRM_ERROR("no scatter/gather memory!\n");
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goto done;
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}
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pci_gart = (u32 *) address;
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max_pages = (gart_info->table_size / sizeof(u32));
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pages = (entry->pages <= max_pages)
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? entry->pages : max_pages;
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for (i = 0; i < pages; i++) {
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/* we need to support large memory configurations */
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entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
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0, PAGE_SIZE, PCI_DMA_TODEVICE);
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if (entry->busaddr[i] == 0) {
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DRM_ERROR("unable to map PCIGART pages!\n");
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drm_ati_pcigart_cleanup(dev, gart_info);
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address = NULL;
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bus_address = 0;
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goto done;
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}
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entry_addr = entry->busaddr[i];
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for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
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gart_insert_page_into_table(gart_info, entry_addr, pci_gart);
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pci_gart++;
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entry_addr += ATI_PCIGART_PAGE_SIZE;
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}
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}
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ret = 1;
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mb();
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done:
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gart_info->addr = address;
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gart_info->bus_addr = bus_address;
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return ret;
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}
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EXPORT_SYMBOL(drm_ati_pcigart_init);
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static int ati_pcigart_needs_unbind_cache_adjust(struct drm_ttm_backend *backend)
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{
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return ((backend->flags & DRM_BE_FLAG_BOUND_CACHED) ? 0 : 1);
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}
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static int ati_pcigart_populate(struct drm_ttm_backend *backend,
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unsigned long num_pages,
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struct page **pages,
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struct page *dummy_read_page)
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{
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struct ati_pcigart_ttm_backend *atipci_be =
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container_of(backend, struct ati_pcigart_ttm_backend, backend);
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atipci_be->pages = pages;
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atipci_be->num_pages = num_pages;
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atipci_be->populated = 1;
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return 0;
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}
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static int ati_pcigart_bind_ttm(struct drm_ttm_backend *backend,
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struct drm_bo_mem_reg *bo_mem)
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{
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struct ati_pcigart_ttm_backend *atipci_be =
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container_of(backend, struct ati_pcigart_ttm_backend, backend);
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off_t j;
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int i;
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struct drm_ati_pcigart_info *info = atipci_be->gart_info;
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u32 *pci_gart;
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dma_addr_t offset = bo_mem->mm_node->start;
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dma_addr_t page_base;
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pci_gart = info->addr;
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j = offset;
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while (j < (offset + atipci_be->num_pages)) {
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if (gart_get_page_from_table(info, pci_gart + j))
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return -EBUSY;
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j++;
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}
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for (i = 0, j = offset; i < atipci_be->num_pages; i++, j++) {
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struct page *cur_page = atipci_be->pages[i];
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/* write value */
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page_base = page_to_phys(cur_page);
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gart_insert_page_into_table(info, page_base, pci_gart + j);
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}
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mb();
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atipci_be->gart_flush_fn(atipci_be->dev);
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atipci_be->bound = 1;
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atipci_be->offset = offset;
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/* need to traverse table and add entries */
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DRM_DEBUG("\n");
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return 0;
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}
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static int ati_pcigart_unbind_ttm(struct drm_ttm_backend *backend)
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{
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struct ati_pcigart_ttm_backend *atipci_be =
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container_of(backend, struct ati_pcigart_ttm_backend, backend);
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struct drm_ati_pcigart_info *info = atipci_be->gart_info;
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unsigned long offset = atipci_be->offset;
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int i;
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off_t j;
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u32 *pci_gart = info->addr;
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if (atipci_be->bound != 1)
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return -EINVAL;
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for (i = 0, j = offset; i < atipci_be->num_pages; i++, j++) {
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*(pci_gart + j) = 0;
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}
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atipci_be->gart_flush_fn(atipci_be->dev);
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atipci_be->bound = 0;
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atipci_be->offset = 0;
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return 0;
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}
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static void ati_pcigart_clear_ttm(struct drm_ttm_backend *backend)
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{
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struct ati_pcigart_ttm_backend *atipci_be =
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container_of(backend, struct ati_pcigart_ttm_backend, backend);
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DRM_DEBUG("\n");
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if (atipci_be->pages) {
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backend->func->unbind(backend);
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atipci_be->pages = NULL;
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}
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atipci_be->num_pages = 0;
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}
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static void ati_pcigart_destroy_ttm(struct drm_ttm_backend *backend)
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{
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struct ati_pcigart_ttm_backend *atipci_be;
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if (backend) {
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DRM_DEBUG("\n");
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atipci_be = container_of(backend, struct ati_pcigart_ttm_backend, backend);
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if (atipci_be) {
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if (atipci_be->pages) {
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backend->func->clear(backend);
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}
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drm_ctl_free(atipci_be, sizeof(*atipci_be), DRM_MEM_TTM);
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}
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}
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}
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static struct drm_ttm_backend_func ati_pcigart_ttm_backend =
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{
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.needs_ub_cache_adjust = ati_pcigart_needs_unbind_cache_adjust,
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.populate = ati_pcigart_populate,
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.clear = ati_pcigart_clear_ttm,
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.bind = ati_pcigart_bind_ttm,
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.unbind = ati_pcigart_unbind_ttm,
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.destroy = ati_pcigart_destroy_ttm,
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};
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struct drm_ttm_backend *ati_pcigart_init_ttm(struct drm_device *dev, struct drm_ati_pcigart_info *info, void (*gart_flush_fn)(struct drm_device *dev))
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{
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struct ati_pcigart_ttm_backend *atipci_be;
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atipci_be = drm_ctl_calloc(1, sizeof (*atipci_be), DRM_MEM_TTM);
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if (!atipci_be)
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return NULL;
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atipci_be->populated = 0;
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atipci_be->backend.func = &ati_pcigart_ttm_backend;
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// atipci_be->backend.mem_type = DRM_BO_MEM_TT;
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atipci_be->gart_info = info;
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atipci_be->gart_flush_fn = gart_flush_fn;
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atipci_be->dev = dev;
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return &atipci_be->backend;
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}
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EXPORT_SYMBOL(ati_pcigart_init_ttm);
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