276 lines
7.8 KiB
C
276 lines
7.8 KiB
C
/*
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* Copyright 2007 Dave Airlie.
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* Copyright 2007 Jérôme Glisse
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Dave Airlie
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* Jerome Glisse <glisse@freedesktop.org>
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*/
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#include "radeon_ms.h"
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#include "amd_legacy_fence.h"
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#define R3XX_FENCE_SEQUENCE_RW_FLUSH 0x80000000u
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static inline int r3xx_fence_emit_sequence(struct drm_device *dev,
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struct drm_radeon_private *dev_priv,
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uint32_t sequence)
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{
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struct legacy_fence *r3xx_fence = dev_priv->fence;
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uint32_t cmd[2];
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int i, r;
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if (sequence & R3XX_FENCE_SEQUENCE_RW_FLUSH) {
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r3xx_fence->sequence_last_flush =
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sequence & ~R3XX_FENCE_SEQUENCE_RW_FLUSH;
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/* Ask flush for VERTEX & FRAGPROG pipeline
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* have 3D idle */
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/* FIXME: proper flush */
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#if 0
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dev_priv->flush_cache(dev);
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#endif
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}
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cmd[0] = CP_PACKET0(dev_priv->fence_reg, 0);
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cmd[1] = sequence;
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for (i = 0; i < dev_priv->usec_timeout; i++) {
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r = radeon_ms_ring_emit(dev, cmd, 2);
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if (!r) {
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dev_priv->irq_emit(dev);
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return 0;
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}
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}
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return -EBUSY;
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}
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static inline uint32_t r3xx_fence_sequence(struct legacy_fence *r3xx_fence)
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{
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r3xx_fence->sequence += 1;
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if (unlikely(r3xx_fence->sequence > 0x7fffffffu)) {
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r3xx_fence->sequence = 1;
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}
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return r3xx_fence->sequence;
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}
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static inline void r3xx_fence_report(struct drm_device *dev,
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struct drm_radeon_private *dev_priv,
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struct legacy_fence *r3xx_fence)
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{
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uint32_t fence_types = DRM_FENCE_TYPE_EXE;
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uint32_t sequence;
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if (dev_priv == NULL) {
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return;
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}
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sequence = mmio_read(dev_priv, dev_priv->fence_reg);
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DRM_INFO("%s pass fence 0x%08x\n", __func__, sequence);
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if (sequence & R3XX_FENCE_SEQUENCE_RW_FLUSH) {
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sequence &= ~R3XX_FENCE_SEQUENCE_RW_FLUSH;
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fence_types |= DRM_AMD_FENCE_TYPE_R;
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fence_types |= DRM_AMD_FENCE_TYPE_W;
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if (sequence == r3xx_fence->sequence_last_flush) {
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r3xx_fence->sequence_last_flush = 0;
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}
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}
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drm_fence_handler(dev, 0, sequence, fence_types, 0);
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r3xx_fence->sequence_last_reported = sequence;
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}
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static void r3xx_fence_flush(struct drm_device *dev, uint32_t class)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct legacy_fence *r3xx_fence = dev_priv->fence;
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uint32_t sequence;
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sequence = r3xx_fence_sequence(r3xx_fence);
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sequence |= R3XX_FENCE_SEQUENCE_RW_FLUSH;
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r3xx_fence_emit_sequence(dev, dev_priv, sequence);
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}
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static void r3xx_fence_poll(struct drm_device *dev, uint32_t fence_class,
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uint32_t waiting_types)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct drm_fence_manager *fm = &dev->fm;
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struct drm_fence_class_manager *fc = &fm->fence_class[fence_class];
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struct legacy_fence *r3xx_fence = dev_priv->fence;
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if (unlikely(!dev_priv)) {
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return;
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}
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/* if there is a RW flush pending then submit new sequence
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* preceded by flush cmds */
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if (fc->pending_flush & (DRM_AMD_FENCE_TYPE_R | DRM_AMD_FENCE_TYPE_W)) {
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r3xx_fence_flush(dev, 0);
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fc->pending_flush &= ~DRM_AMD_FENCE_TYPE_R;
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fc->pending_flush &= ~DRM_AMD_FENCE_TYPE_W;
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}
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r3xx_fence_report(dev, dev_priv, r3xx_fence);
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return;
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}
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static int r3xx_fence_emit(struct drm_device *dev, uint32_t class,
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uint32_t flags, uint32_t *sequence,
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uint32_t *native_type)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct legacy_fence *r3xx_fence = dev_priv->fence;
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uint32_t tmp;
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if (!dev_priv || dev_priv->cp_ready != 1) {
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return -EINVAL;
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}
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*sequence = tmp = r3xx_fence_sequence(r3xx_fence);
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*native_type = DRM_FENCE_TYPE_EXE;
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if (flags & DRM_AMD_FENCE_FLAG_FLUSH) {
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*native_type |= DRM_AMD_FENCE_TYPE_R;
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*native_type |= DRM_AMD_FENCE_TYPE_W;
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tmp |= R3XX_FENCE_SEQUENCE_RW_FLUSH;
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}
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DRM_INFO("%s emit fence 0x%08x\n", __func__, tmp);
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return r3xx_fence_emit_sequence(dev, dev_priv, tmp);
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}
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static int r3xx_fence_has_irq(struct drm_device *dev,
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uint32_t class, uint32_t type)
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{
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const uint32_t type_irq_mask = DRM_FENCE_TYPE_EXE |
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DRM_AMD_FENCE_TYPE_R |
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DRM_AMD_FENCE_TYPE_W;
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/*
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* We have an irq for EXE & RW fence.
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*/
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if (class == 0 && (type & type_irq_mask)) {
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return 1;
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}
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return 0;
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}
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static uint32_t r3xx_fence_needed_flush(struct drm_fence_object *fence)
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{
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struct drm_device *dev = fence->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct legacy_fence *r3xx_fence = dev_priv->fence;
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struct drm_fence_driver *driver = dev->driver->fence_driver;
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uint32_t flush_types, diff;
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flush_types = fence->waiting_types &
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~(DRM_FENCE_TYPE_EXE | fence->signaled_types);
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if (flush_types == 0 || ((flush_types & ~fence->native_types) == 0)) {
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return 0;
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}
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if (unlikely(dev_priv == NULL)) {
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return 0;
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}
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if (r3xx_fence->sequence_last_flush) {
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diff = (r3xx_fence->sequence_last_flush - fence->sequence) &
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driver->sequence_mask;
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if (diff < driver->wrap_diff) {
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return 0;
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}
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}
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return flush_types;
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}
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static int r3xx_fence_wait(struct drm_fence_object *fence,
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int lazy, int interruptible, uint32_t mask)
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{
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struct drm_device *dev = fence->dev;
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struct drm_fence_manager *fm = &dev->fm;
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struct drm_fence_class_manager *fc = &fm->fence_class[0];
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int r;
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drm_fence_object_flush(fence, mask);
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if (likely(interruptible)) {
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r = wait_event_interruptible_timeout(
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fc->fence_queue,
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drm_fence_object_signaled(fence, DRM_FENCE_TYPE_EXE),
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3 * DRM_HZ);
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} else {
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r = wait_event_timeout(
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fc->fence_queue,
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drm_fence_object_signaled(fence, DRM_FENCE_TYPE_EXE),
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3 * DRM_HZ);
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}
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if (unlikely(r == -ERESTARTSYS)) {
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return -EAGAIN;
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}
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if (unlikely(r == 0)) {
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return -EBUSY;
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}
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if (likely(mask == DRM_FENCE_TYPE_EXE ||
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drm_fence_object_signaled(fence, mask))) {
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return 0;
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}
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/*
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* Poll for sync flush completion.
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*/
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return drm_fence_wait_polling(fence, lazy, interruptible,
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mask, 3 * DRM_HZ);
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}
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struct drm_fence_driver r3xx_fence_driver = {
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.num_classes = 1,
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.wrap_diff = (1 << 29),
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.flush_diff = (1 << 28),
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.sequence_mask = 0x7fffffffU,
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.has_irq = r3xx_fence_has_irq,
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.emit = r3xx_fence_emit,
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.flush = r3xx_fence_flush,
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.poll = r3xx_fence_poll,
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.needed_flush = r3xx_fence_needed_flush,
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.wait = r3xx_fence_wait,
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};
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/* this are used by the buffer object code */
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int r3xx_fence_types(struct drm_buffer_object *bo,
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uint32_t *class, uint32_t *type)
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{
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*class = 0;
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if (bo->mem.flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE)) {
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*type = DRM_FENCE_TYPE_EXE |
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DRM_AMD_FENCE_TYPE_R |
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DRM_AMD_FENCE_TYPE_W;
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} else {
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*type = DRM_FENCE_TYPE_EXE;
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}
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return 0;
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}
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/* this are used by the irq code */
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void r3xx_fence_handler(struct drm_device * dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct drm_fence_manager *fm = &dev->fm;
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struct drm_fence_class_manager *fc = &fm->fence_class[0];
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if (unlikely(dev_priv == NULL)) {
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return;
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}
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write_lock(&fm->lock);
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r3xx_fence_poll(dev, 0, fc->waiting_types);
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write_unlock(&fm->lock);
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}
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