605 lines
16 KiB
C
605 lines
16 KiB
C
/*
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* Copyright (C) 2006 Ben Skeggs.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/*
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* Authors:
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* Ben Skeggs <darktama@iinet.net.au>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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/* TODO
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* - Check object class, deny unsafe objects (add card-specific versioning?)
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* - Get rid of DMA object creation, this should be wrapped by MM routines.
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*/
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/* Translate a RAMIN offset into a value the card understands, will be useful
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* in the future when we can access more instance ram which isn't mapped into
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* the PRAMIN aperture
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*/
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uint32_t
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nouveau_chip_instance_get(drm_device_t *dev, struct mem_block *mem)
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{
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uint32_t inst = (uint32_t)mem->start >> 4;
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DRM_DEBUG("****** on-chip instance for 0x%016llx = 0x%08x\n",
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mem->start, inst);
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return inst;
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}
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static void
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nouveau_object_link(drm_device_t *dev, struct nouveau_object *obj)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_fifo *chan = &dev_priv->fifos[obj->channel];
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if (!chan->objs) {
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chan->objs = obj;
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return;
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}
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obj->prev = NULL;
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obj->next = chan->objs;
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chan->objs->prev = obj;
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chan->objs = obj;
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}
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static void
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nouveau_object_unlink(drm_device_t *dev, struct nouveau_object *obj)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_fifo *chan = &dev_priv->fifos[obj->channel];
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if (obj->prev == NULL) {
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if (obj->next)
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obj->next->prev = NULL;
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chan->objs = obj->next;
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} else if (obj->next == NULL) {
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if (obj->prev)
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obj->prev->next = NULL;
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} else {
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obj->prev->next = obj->next;
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obj->next->prev = obj->prev;
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}
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}
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static struct nouveau_object *
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nouveau_object_handle_find(drm_device_t *dev, int channel, uint32_t handle)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_fifo *chan = &dev_priv->fifos[channel];
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struct nouveau_object *obj = chan->objs;
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DRM_DEBUG("Looking for handle 0x%08x\n", handle);
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while (obj) {
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if (obj->handle == handle)
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return obj;
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obj = obj->next;
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}
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DRM_DEBUG("...couldn't find handle\n");
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return NULL;
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}
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/* NVidia uses context objects to drive drawing operations.
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Context objects can be selected into 8 subchannels in the FIFO,
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and then used via DMA command buffers.
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A context object is referenced by a user defined handle (CARD32). The HW
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looks up graphics objects in a hash table in the instance RAM.
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An entry in the hash table consists of 2 CARD32. The first CARD32 contains
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the handle, the second one a bitfield, that contains the address of the
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object in instance RAM.
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The format of the second CARD32 seems to be:
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NV4 to NV30:
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15: 0 instance_addr >> 4
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17:16 engine (here uses 1 = graphics)
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28:24 channel id (here uses 0)
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31 valid (use 1)
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NV40:
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15: 0 instance_addr >> 4 (maybe 19-0)
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21:20 engine (here uses 1 = graphics)
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I'm unsure about the other bits, but using 0 seems to work.
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The key into the hash table depends on the object handle and channel id and
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is given as:
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*/
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static uint32_t
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nouveau_ht_handle_hash(drm_device_t *dev, int channel, uint32_t handle)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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uint32_t hash = 0;
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int i;
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for (i=32;i>0;i-=dev_priv->ramht_bits) {
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hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
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handle >>= dev_priv->ramht_bits;
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}
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hash ^= channel << (dev_priv->ramht_bits - 4);
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return hash << 3;
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}
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static int
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nouveau_ht_object_insert(drm_device_t* dev, int channel, uint32_t handle,
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struct nouveau_object *obj)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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int ht_base = NV_RAMIN + dev_priv->ramht_offset;
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int ht_end = ht_base + dev_priv->ramht_size;
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int o_ofs, ofs;
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obj->handle = handle;
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o_ofs = ofs = nouveau_ht_handle_hash(dev, channel, obj->handle);
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while (NV_READ(ht_base + ofs) || NV_READ(ht_base + ofs + 4)) {
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ofs += 8;
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if (ofs == dev_priv->ramht_size) ofs = 0;
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if (ofs == o_ofs) {
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DRM_ERROR("no free hash table entries\n");
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return 1;
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}
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}
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ofs += ht_base;
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DRM_DEBUG("Channel %d - Handle 0x%08x at 0x%08x\n",
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channel, obj->handle, ofs);
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NV_WRITE(NV_RAMHT_HANDLE_OFFSET + ofs, obj->handle);
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if (dev_priv->card_type >= NV_40)
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NV_WRITE(NV_RAMHT_CONTEXT_OFFSET + ofs,
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(channel << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |
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(obj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT) |
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nouveau_chip_instance_get(dev, obj->instance)
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);
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else
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NV_WRITE(NV_RAMHT_CONTEXT_OFFSET + ofs,
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NV_RAMHT_CONTEXT_VALID |
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(channel << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |
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(obj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT) |
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nouveau_chip_instance_get(dev, obj->instance)
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);
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obj->ht_loc = ofs;
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return 0;
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}
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static void nouveau_hash_table_remove(drm_device_t* dev,
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struct nouveau_object *obj)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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DRM_DEBUG("Remove handle 0x%08x at 0x%08x from HT\n",
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obj->handle, obj->ht_loc);
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if (obj->ht_loc) {
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DRM_DEBUG("... HT entry was: 0x%08x/0x%08x\n",
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NV_READ(obj->ht_loc), NV_READ(obj->ht_loc+4));
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NV_WRITE(obj->ht_loc , 0x00000000);
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NV_WRITE(obj->ht_loc+4, 0x00000000);
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}
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}
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static struct nouveau_object *
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nouveau_object_instance_alloc(drm_device_t* dev, int channel)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_object *obj;
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/* Create object struct */
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obj = drm_calloc(1, sizeof(struct nouveau_object), DRM_MEM_DRIVER);
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if (!obj) {
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DRM_ERROR("couldn't alloc memory for object\n");
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return NULL;
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}
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/* Allocate instance memory */
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obj->instance = nouveau_instmem_alloc(dev,
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(dev_priv->card_type >= NV_40 ? 32 : 16), 4);
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if (!obj->instance) {
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DRM_ERROR("couldn't alloc RAMIN for object\n");
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drm_free(obj, sizeof(struct nouveau_object), DRM_MEM_DRIVER);
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return NULL;
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}
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/* Bind object to channel */
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obj->channel = channel;
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obj->handle = ~0;
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nouveau_object_link(dev, obj);
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return obj;
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}
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static void
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nouveau_object_instance_free(drm_device_t *dev, struct nouveau_object *obj)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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int i;
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/* Unbind object from channel */
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nouveau_object_unlink(dev, obj);
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/* Clean RAMIN entry */
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DRM_DEBUG("Instance entry for 0x%08x"
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"(engine %d, class 0x%x) before destroy:\n",
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obj->handle, obj->engine, obj->class);
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for (i=0; i<(obj->instance->size/4); i++) {
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DRM_DEBUG(" +0x%02x: 0x%08x\n", (i*4),
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INSTANCE_RD(obj->instance, i));
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INSTANCE_WR(obj->instance, i, 0x00000000);
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}
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/* Free RAMIN */
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nouveau_instmem_free(dev, obj->instance);
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}
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/*
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DMA objects are used to reference a piece of memory in the
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framebuffer, PCI or AGP address space. Each object is 16 bytes big
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and looks as follows:
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entry[0]
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11:0 class (seems like I can always use 0 here)
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12 page table present?
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13 page entry linear?
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15:14 access: 0 rw, 1 ro, 2 wo
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17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
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31:20 dma adjust (bits 0-11 of the address)
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entry[1]
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dma limit
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entry[2]
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1 0 readonly, 1 readwrite
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31:12 dma frame address (bits 12-31 of the address)
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Non linear page tables seem to need a list of frame addresses afterwards,
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the rivatv project has some info on this.
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The method below creates a DMA object in instance RAM and returns a handle
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to it that can be used to set up context objects.
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*/
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struct nouveau_object *
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nouveau_object_dma_create(drm_device_t* dev, int channel, int class,
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uint32_t offset, uint32_t size,
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int access, int target)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_object *obj;
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uint32_t frame, adjust;
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uint32_t pte_flags = 0;
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DRM_DEBUG("offset:0x%08x, size:0x%08x, target:%d, access:%d\n",
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offset, size, target, access);
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switch (target) {
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case NV_DMA_TARGET_AGP:
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offset += dev_priv->agp_phys;
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break;
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default:
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break;
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}
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switch (access) {
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case NV_DMA_ACCESS_RO:
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break;
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case NV_DMA_ACCESS_WO:
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case NV_DMA_ACCESS_RW:
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pte_flags |= (1 << 1);
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break;
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default:
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DRM_ERROR("invalid access mode=%d\n", access);
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return NULL;
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}
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frame = offset & ~0x00000FFF;
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adjust = offset & 0x00000FFF;
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obj = nouveau_object_instance_alloc(dev, channel);
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if (!obj) {
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DRM_ERROR("couldn't allocate DMA object\n");
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return obj;
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}
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obj->engine = 0;
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obj->class = class;
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INSTANCE_WR(obj->instance, 0, ((1<<12) | (1<<13) |
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(adjust << 20) |
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(access << 14) |
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(target << 16) |
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class));
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INSTANCE_WR(obj->instance, 1, size-1);
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INSTANCE_WR(obj->instance, 2, frame | pte_flags);
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INSTANCE_WR(obj->instance, 3, frame | pte_flags);
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return obj;
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}
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/* Context objects in the instance RAM have the following structure.
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* On NV40 they are 32 byte long, on NV30 and smaller 16 bytes.
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NV4 - NV30:
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entry[0]
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11:0 class
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12 chroma key enable
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13 user clip enable
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14 swizzle enable
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17:15 patch config:
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scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre
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18 synchronize enable
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19 endian: 1 big, 0 little
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21:20 dither mode
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23 single step enable
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24 patch status: 0 invalid, 1 valid
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25 context_surface 0: 1 valid
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26 context surface 1: 1 valid
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27 context pattern: 1 valid
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28 context rop: 1 valid
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29,30 context beta, beta4
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entry[1]
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7:0 mono format
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15:8 color format
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31:16 notify instance address
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entry[2]
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15:0 dma 0 instance address
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31:16 dma 1 instance address
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entry[3]
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dma method traps
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NV40:
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No idea what the exact format is. Here's what can be deducted:
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entry[0]:
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11:0 class (maybe uses more bits here?)
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17 user clip enable
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21:19 patch config
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25 patch status valid ?
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entry[1]:
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15:0 DMA notifier (maybe 20:0)
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entry[2]:
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15:0 DMA 0 instance (maybe 20:0)
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24 big endian
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entry[3]:
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15:0 DMA 1 instance (maybe 20:0)
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entry[4]:
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entry[5]:
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set to 0?
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*/
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struct nouveau_object *
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nouveau_object_gr_create(drm_device_t* dev, int channel, int class)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_object *obj;
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DRM_DEBUG("class=%x\n", class);
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obj = nouveau_object_instance_alloc(dev, channel);
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if (!obj) {
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DRM_ERROR("couldn't allocate context object\n");
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return obj;
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}
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obj->engine = 1;
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obj->class = class;
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switch (class) {
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case NV_CLASS_NULL:
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INSTANCE_WR(obj->instance, 0, 0x00001030);
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INSTANCE_WR(obj->instance, 1, 0xFFFFFFFF);
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INSTANCE_WR(obj->instance, 2, 0x00000000);
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INSTANCE_WR(obj->instance, 2, 0x00000000);
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break;
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default:
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if (dev_priv->card_type >= NV_40) {
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INSTANCE_WR(obj->instance, 0, obj->class);
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INSTANCE_WR(obj->instance, 1, 0x00000000);
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#ifdef __BIG_ENDIAN
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INSTANCE_WR(obj->instance, 2, 0x01000000);
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#else
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INSTANCE_WR(obj->instance, 2, 0x00000000);
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#endif
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INSTANCE_WR(obj->instance, 3, 0x00000000);
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INSTANCE_WR(obj->instance, 4, 0x00000000);
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INSTANCE_WR(obj->instance, 5, 0x00000000);
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INSTANCE_WR(obj->instance, 6, 0x00000000);
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INSTANCE_WR(obj->instance, 7, 0x00000000);
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} else {
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#ifdef __BIG_ENDIAN
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INSTANCE_WR(obj->instance, 0, obj->class | 0x00080000);
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#else
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INSTANCE_WR(obj->instance, 0, obj->class);
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#endif
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INSTANCE_WR(obj->instance, 1, 0x00000000);
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INSTANCE_WR(obj->instance, 2, 0x00000000);
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INSTANCE_WR(obj->instance, 3, 0x00000000);
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}
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}
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return obj;
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}
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void
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nouveau_object_free(drm_device_t *dev, struct nouveau_object *obj)
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{
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nouveau_object_instance_free(dev, obj);
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if (obj->handle != ~0)
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nouveau_hash_table_remove(dev, obj);
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drm_free(obj, sizeof(struct nouveau_object), DRM_MEM_DRIVER);
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}
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void nouveau_object_cleanup(drm_device_t *dev, int channel)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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while (dev_priv->fifos[channel].objs) {
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nouveau_object_free(dev, dev_priv->fifos[channel].objs);
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}
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}
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int nouveau_ioctl_object_init(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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drm_nouveau_object_init_t init;
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struct nouveau_object *obj;
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DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_object_init_t __user *)
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data, sizeof(init));
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if (!nouveau_fifo_owner(dev, filp, init.channel)) {
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DRM_ERROR("pid %d doesn't own channel %d\n",
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DRM_CURRENTPID, init.channel);
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return DRM_ERR(EINVAL);
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}
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//FIXME: check args, only allow trusted objects to be created
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if (nouveau_object_handle_find(dev, init.channel, init.handle)) {
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DRM_ERROR("Channel %d: handle 0x%08x already exists\n",
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init.channel, init.handle);
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return DRM_ERR(EINVAL);
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}
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obj = nouveau_object_gr_create(dev, init.channel, init.class);
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if (!obj)
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return DRM_ERR(ENOMEM);
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if (nouveau_ht_object_insert(dev, init.channel, init.handle, obj)) {
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nouveau_object_free(dev, obj);
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return DRM_ERR(ENOMEM);
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}
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return 0;
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}
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static int
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nouveau_dma_object_check_access(drm_device_t *dev,
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drm_nouveau_dma_object_init_t *init)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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uint64_t limit;
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/* Check for known DMA object classes */
|
|
switch (init->class) {
|
|
case NV_CLASS_DMA_IN_MEMORY:
|
|
case NV_CLASS_DMA_FROM_MEMORY:
|
|
case NV_CLASS_DMA_TO_MEMORY:
|
|
break;
|
|
default:
|
|
DRM_ERROR("invalid class = 0x%x\n", init->class);
|
|
return DRM_ERR(EPERM);
|
|
}
|
|
|
|
/* Check access mode, and translate to NV_DMA_ACCESS_* */
|
|
switch (init->access) {
|
|
case NOUVEAU_MEM_ACCESS_RO:
|
|
init->access = NV_DMA_ACCESS_RO;
|
|
break;
|
|
case NOUVEAU_MEM_ACCESS_WO:
|
|
init->access = NV_DMA_ACCESS_WO;
|
|
break;
|
|
case NOUVEAU_MEM_ACCESS_RW:
|
|
init->access = NV_DMA_ACCESS_RW;
|
|
break;
|
|
default:
|
|
DRM_ERROR("invalid access mode = %d\n", init->access);
|
|
return DRM_ERR(EPERM);
|
|
}
|
|
|
|
/* Check that request is within the allowed limits of "target" */
|
|
switch (init->target) {
|
|
case NOUVEAU_MEM_FB:
|
|
limit = dev_priv->fb_available_size;
|
|
init->target = NV_DMA_TARGET_VIDMEM;
|
|
break;
|
|
case NOUVEAU_MEM_AGP:
|
|
limit = dev_priv->agp_available_size;
|
|
init->target = NV_DMA_TARGET_AGP;
|
|
break;
|
|
default:
|
|
DRM_ERROR("invalid target = 0x%x\n", init->target);
|
|
return DRM_ERR(EPERM);
|
|
}
|
|
|
|
if ((init->offset > limit) || (init->offset + init->size) > limit) {
|
|
DRM_ERROR("access out of allowed range (%d,0x%08x,0x%08x)\n",
|
|
init->target, init->offset, init->size);
|
|
return DRM_ERR(EPERM);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int nouveau_ioctl_dma_object_init(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
drm_nouveau_dma_object_init_t init;
|
|
struct nouveau_object *obj;
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_dma_object_init_t __user *)
|
|
data, sizeof(init));
|
|
|
|
if (!nouveau_fifo_owner(dev, filp, init.channel)) {
|
|
DRM_ERROR("pid %d doesn't own channel %d\n",
|
|
DRM_CURRENTPID, init.channel);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
if (nouveau_dma_object_check_access(dev, &init))
|
|
return DRM_ERR(EPERM);
|
|
|
|
if (nouveau_object_handle_find(dev, init.channel, init.handle)) {
|
|
DRM_ERROR("Channel %d: handle 0x%08x already exists\n",
|
|
init.channel, init.handle);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
obj = nouveau_object_dma_create(dev, init.channel, init.class,
|
|
init.offset, init.size,
|
|
init.access, init.target);
|
|
if (!obj)
|
|
return DRM_ERR(ENOMEM);
|
|
|
|
obj->handle = init.handle;
|
|
if (nouveau_ht_object_insert(dev, init.channel, init.handle, obj)) {
|
|
nouveau_object_free(dev, obj);
|
|
return DRM_ERR(ENOMEM);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|