398 lines
11 KiB
C
398 lines
11 KiB
C
/*
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* Copyright (C) 2006 Ben Skeggs.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/*
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* Authors:
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* Ben Skeggs <darktama@iinet.net.au>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_reg.h"
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void nouveau_irq_preinstall(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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DRM_DEBUG("IRQ: preinst\n");
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/* Disable/Clear PFIFO interrupts */
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NV_WRITE(NV03_PFIFO_INTR_EN_0, 0);
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NV_WRITE(NV03_PMC_INTR_0, 0xFFFFFFFF);
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/* Disable/Clear PGRAPH interrupts */
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if (dev_priv->card_type<NV_40)
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NV_WRITE(NV03_PGRAPH_INTR_EN, 0);
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else
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NV_WRITE(NV40_PGRAPH_INTR_EN, 0);
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NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
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#if 0
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/* Disable/Clear CRTC0/1 interrupts */
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NV_WRITE(NV_CRTC0_INTEN, 0);
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NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
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NV_WRITE(NV_CRTC1_INTEN, 0);
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NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
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#endif
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/* Master disable */
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NV_WRITE(NV03_PMC_INTR_EN_0, 0);
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}
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void nouveau_irq_postinstall(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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DRM_DEBUG("IRQ: postinst\n");
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/* Enable PFIFO error reporting */
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NV_WRITE(NV03_PFIFO_INTR_EN_0 ,
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NV_PFIFO_INTR_CACHE_ERROR |
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NV_PFIFO_INTR_RUNOUT |
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NV_PFIFO_INTR_RUNOUT_OVERFLOW |
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NV_PFIFO_INTR_DMA_PUSHER |
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NV_PFIFO_INTR_DMA_PT |
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NV_PFIFO_INTR_SEMAPHORE |
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NV_PFIFO_INTR_ACQUIRE_TIMEOUT
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);
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NV_WRITE(NV03_PMC_INTR_0, 0xFFFFFFFF);
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/* Enable PGRAPH interrupts */
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if (dev_priv->card_type<NV_40)
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NV_WRITE(NV03_PGRAPH_INTR_EN,
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NV_PGRAPH_INTR_NOTIFY |
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NV_PGRAPH_INTR_MISSING_HW |
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NV_PGRAPH_INTR_CONTEXT_SWITCH |
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NV_PGRAPH_INTR_BUFFER_NOTIFY |
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NV_PGRAPH_INTR_ERROR
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);
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else
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NV_WRITE(NV40_PGRAPH_INTR_EN,
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NV_PGRAPH_INTR_NOTIFY |
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NV_PGRAPH_INTR_MISSING_HW |
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NV_PGRAPH_INTR_CONTEXT_SWITCH |
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NV_PGRAPH_INTR_BUFFER_NOTIFY |
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NV_PGRAPH_INTR_ERROR
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);
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NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
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#if 0
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/* Enable CRTC0/1 interrupts */
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NV_WRITE(NV_CRTC0_INTEN, NV_CRTC_INTR_VBLANK);
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NV_WRITE(NV_CRTC1_INTEN, NV_CRTC_INTR_VBLANK);
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#endif
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/* Master enable */
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NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
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}
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void nouveau_irq_uninstall(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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DRM_DEBUG("IRQ: uninst\n");
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/* Disable PFIFO interrupts */
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NV_WRITE(NV03_PFIFO_INTR_EN_0, 0);
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/* Disable PGRAPH interrupts */
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if (dev_priv->card_type<NV_40)
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NV_WRITE(NV03_PGRAPH_INTR_EN, 0);
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else
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NV_WRITE(NV40_PGRAPH_INTR_EN, 0);
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#if 0
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/* Disable CRTC0/1 interrupts */
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NV_WRITE(NV_CRTC0_INTEN, 0);
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NV_WRITE(NV_CRTC1_INTEN, 0);
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#endif
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/* Master disable */
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NV_WRITE(NV03_PMC_INTR_EN_0, 0);
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}
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static void nouveau_fifo_irq_handler(drm_device_t *dev)
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{
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uint32_t status, chmode, chstat, channel;
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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status = NV_READ(NV03_PMC_INTR_0);
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if (!status)
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return;
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chmode = NV_READ(NV04_PFIFO_MODE);
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chstat = NV_READ(NV04_PFIFO_DMA);
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channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
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DRM_DEBUG("NV: PFIFO interrupt! Channel=%d, INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", channel, status, chmode, chstat);
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if (status & NV_PFIFO_INTR_CACHE_ERROR) {
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uint32_t c1get, c1method, c1data;
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DRM_ERROR("NV: PFIFO error interrupt\n");
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c1get = NV_READ(NV03_PFIFO_CACHE1_GET) >> 2;
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if (dev_priv->card_type < NV_40) {
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/* Untested, so it may not work.. */
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c1method = NV_READ(NV04_PFIFO_CACHE1_METHOD(c1get));
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c1data = NV_READ(NV04_PFIFO_CACHE1_DATA(c1get));
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} else {
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c1method = NV_READ(NV40_PFIFO_CACHE1_METHOD(c1get));
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c1data = NV_READ(NV40_PFIFO_CACHE1_DATA(c1get));
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}
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DRM_ERROR("NV: Channel %d/%d - Method 0x%04x, Data 0x%08x\n",
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channel, (c1method >> 13) & 7,
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c1method & 0x1ffc, c1data
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);
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status &= ~NV_PFIFO_INTR_CACHE_ERROR;
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NV_WRITE(NV03_PMC_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
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}
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if (status & NV_PFIFO_INTR_DMA_PUSHER) {
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DRM_INFO("NV: PFIFO DMA pusher interrupt\n");
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status &= ~NV_PFIFO_INTR_DMA_PUSHER;
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NV_WRITE(NV03_PMC_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);
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NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
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if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)!=NV_READ(NV04_PFIFO_CACHE1_DMA_GET))
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{
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uint32_t getval=NV_READ(NV04_PFIFO_CACHE1_DMA_GET)+4;
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NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET,getval);
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}
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}
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if (status) {
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DRM_INFO("NV: unknown PFIFO interrupt. status=0x%08x\n", status);
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NV_WRITE(NV03_PMC_INTR_0, status);
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}
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NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
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}
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#if 0
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static void nouveau_nv04_context_switch(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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uint32_t channel,i;
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uint32_t max=0;
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NV_WRITE(NV04_PGRAPH_FIFO,0x0);
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channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
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//DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV03_PFIFO_CACHE1_PUSH1));
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//DRM_INFO("currently on channel %d\n",channel);
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for (i=0;i<nouveau_fifo_number(dev);i++)
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if ((dev_priv->fifos[i].used)&&(i!=channel)) {
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uint32_t put,get,pending;
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//put=NV_READ(dev_priv->ramfc_offset+i*32);
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//get=NV_READ(dev_priv->ramfc_offset+4+i*32);
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put=NV_READ(NV03_FIFO_REGS_DMAPUT(i));
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get=NV_READ(NV03_FIFO_REGS_DMAGET(i));
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pending=NV_READ(NV04_PFIFO_DMA);
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//DRM_INFO("Channel %d (put/get %x/%x)\n",i,put,get);
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/* mark all pending channels as such */
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if ((put!=get)&!(pending&(1<<i)))
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{
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pending|=(1<<i);
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NV_WRITE(NV04_PFIFO_DMA,pending);
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}
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max++;
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}
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nouveau_wait_for_idle(dev);
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#if 1
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/* 2-channel commute */
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// NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,channel|0x100);
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if (channel==0)
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channel=1;
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else
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channel=0;
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// dev_priv->cur_fifo=channel;
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NV_WRITE(NV04_PFIFO_NEXT_CHANNEL,channel|0x100);
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#endif
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//NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,max|0x100);
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//NV_WRITE(0x2050,max|0x100);
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NV_WRITE(NV04_PGRAPH_FIFO,0x1);
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}
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#endif
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static void nouveau_pgraph_irq_handler(drm_device_t *dev)
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{
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uint32_t status;
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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status = NV_READ(NV03_PGRAPH_INTR);
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if (!status)
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return;
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if (status & NV_PGRAPH_INTR_NOTIFY) {
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uint32_t nsource, nstatus, instance, notify;
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DRM_DEBUG("NV: PGRAPH notify interrupt\n");
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nstatus = NV_READ(0x00400104);
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nsource = NV_READ(0x00400108);
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DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
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instance = NV_READ(0x00400158);
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notify = NV_READ(0x00400150) >> 16;
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DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", nsource, nstatus);
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status &= ~NV_PGRAPH_INTR_NOTIFY;
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NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
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}
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if (status & NV_PGRAPH_INTR_BUFFER_NOTIFY) {
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uint32_t nsource, nstatus, instance, notify;
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DRM_DEBUG("NV: PGRAPH buffer notify interrupt\n");
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nstatus = NV_READ(0x00400104);
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nsource = NV_READ(0x00400108);
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DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
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instance = NV_READ(0x00400158);
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notify = NV_READ(0x00400150) >> 16;
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DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", instance, notify);
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status &= ~NV_PGRAPH_INTR_BUFFER_NOTIFY;
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NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_BUFFER_NOTIFY);
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}
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if (status & NV_PGRAPH_INTR_MISSING_HW) {
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DRM_ERROR("NV: PGRAPH missing hw interrupt\n");
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status &= ~NV_PGRAPH_INTR_MISSING_HW;
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NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_MISSING_HW);
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}
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if (status & NV_PGRAPH_INTR_ERROR) {
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uint32_t nsource, nstatus, instance;
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uint32_t address;
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uint32_t channel;
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uint32_t method, subc, data;
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DRM_ERROR("NV: PGRAPH error interrupt\n");
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nstatus = NV_READ(0x00400104);
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nsource = NV_READ(0x00400108);
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DRM_ERROR("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
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instance = NV_READ(0x00400158);
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DRM_ERROR("instance:0x%08x\n", instance);
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address = NV_READ(0x400704);
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data = NV_READ(0x400708);
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channel = (address >> 20) & 0x1F;
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subc = (address >> 16) & 0x7;
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method = address & 0x1FFC;
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DRM_DEBUG("NV: 0x400704 = 0x%08x\n", address);
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DRM_ERROR("NV: Channel %d/%d (class 0x%04x) -"
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"Method 0x%04x, Data 0x%08x\n",
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channel, subc,
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NV_READ(0x400160+subc*4) & 0xFFFF,
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method, data
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);
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status &= ~NV_PGRAPH_INTR_ERROR;
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NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
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}
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if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
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uint32_t channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
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DRM_INFO("NV: PGRAPH context switch interrupt channel %x\n",channel);
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switch(dev_priv->card_type)
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{
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case NV_04:
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case NV_05:
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nouveau_nv04_context_switch(dev);
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break;
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case NV_10:
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nouveau_nv10_context_switch(dev);
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break;
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case NV_20:
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case NV_30:
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nouveau_nv20_context_switch(dev);
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break;
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default:
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DRM_INFO("NV: Context switch not implemented\n");
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break;
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}
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status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
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NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
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}
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if (status) {
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DRM_INFO("NV: Unknown PGRAPH interrupt! STAT=0x%08x\n", status);
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NV_WRITE(NV03_PGRAPH_INTR, status);
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}
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NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
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}
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static void nouveau_crtc_irq_handler(drm_device_t *dev, int crtc)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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if (crtc&1) {
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NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
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}
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if (crtc&2) {
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NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
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}
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}
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irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS)
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{
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drm_device_t *dev = (drm_device_t*)arg;
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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uint32_t status;
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status = NV_READ(NV03_PMC_INTR_0);
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if (!status)
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return IRQ_NONE;
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DRM_DEBUG("PMC INTSTAT: 0x%08x\n", status);
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if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
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nouveau_fifo_irq_handler(dev);
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status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
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}
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if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
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nouveau_pgraph_irq_handler(dev);
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status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
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}
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if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
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nouveau_crtc_irq_handler(dev, (status>>24)&3);
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status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
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}
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if (status)
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DRM_ERROR("Unhandled PMC INTR status bits 0x%08x\n", status);
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return IRQ_HANDLED;
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}
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