534 lines
14 KiB
C
534 lines
14 KiB
C
/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <unistd.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include "CUnit/Basic.h"
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#include "amdgpu_test.h"
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#include "amdgpu_drm.h"
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#include "amdgpu_internal.h"
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#define IB_SIZE 4096
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#define MAX_RESOURCES 8
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#define DMA_SIZE 4097
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#define DMA_DATA_BYTE 0xea
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static bool do_p2p;
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static amdgpu_device_handle executing_device_handle;
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static uint32_t executing_device_major_version;
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static uint32_t executing_device_minor_version;
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static amdgpu_device_handle peer_exporting_device_handle;
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static uint32_t peer_exporting_device_major_version;
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static uint32_t peer_exporting_device_minor_version;
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static amdgpu_context_handle context_handle;
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static amdgpu_bo_handle ib_handle;
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static uint32_t *ib_cpu;
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static uint64_t ib_mc_address;
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static amdgpu_va_handle ib_va_handle;
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static uint32_t num_dword;
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static amdgpu_bo_handle resources[MAX_RESOURCES];
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static unsigned num_resources;
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static uint8_t* reference_data;
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static void amdgpu_cp_dma_host_to_vram(void);
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static void amdgpu_cp_dma_vram_to_host(void);
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static void amdgpu_cp_dma_p2p_vram_to_vram(void);
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static void amdgpu_cp_dma_p2p_host_to_vram(void);
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static void amdgpu_cp_dma_p2p_vram_to_host(void);
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/**
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* Tests in cp dma test suite
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*/
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CU_TestInfo cp_dma_tests[] = {
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{ "CP DMA write Host to VRAM", amdgpu_cp_dma_host_to_vram },
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{ "CP DMA write VRAM to Host", amdgpu_cp_dma_vram_to_host },
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{ "Peer to Peer CP DMA write VRAM to VRAM", amdgpu_cp_dma_p2p_vram_to_vram },
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{ "Peer to Peer CP DMA write Host to VRAM", amdgpu_cp_dma_p2p_host_to_vram },
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{ "Peer to Peer CP DMA write VRAM to Host", amdgpu_cp_dma_p2p_vram_to_host },
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CU_TEST_INFO_NULL,
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};
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struct amdgpu_cp_dma_bo{
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amdgpu_bo_handle buf_handle;
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amdgpu_va_handle va_handle;
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uint64_t gpu_va;
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uint64_t size;
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};
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static int allocate_bo_and_va(amdgpu_device_handle dev,
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uint64_t size, uint64_t alignment,
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uint32_t heap, uint64_t alloc_flags,
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struct amdgpu_cp_dma_bo *bo) {
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struct amdgpu_bo_alloc_request request = {};
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amdgpu_bo_handle buf_handle;
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amdgpu_va_handle va_handle;
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uint64_t vmc_addr;
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int r;
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request.alloc_size = size;
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request.phys_alignment = alignment;
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request.preferred_heap = heap;
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request.flags = alloc_flags;
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r = amdgpu_bo_alloc(dev, &request, &buf_handle);
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if (r)
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goto error_bo_alloc;
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r = amdgpu_va_range_alloc(dev, amdgpu_gpu_va_range_general,
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size, alignment, 0,
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&vmc_addr, &va_handle, 0);
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if (r)
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goto error_va_alloc;
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r = amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr,
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AMDGPU_VM_PAGE_READABLE |
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AMDGPU_VM_PAGE_WRITEABLE |
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AMDGPU_VM_PAGE_EXECUTABLE,
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AMDGPU_VA_OP_MAP);
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if (r)
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goto error_va_map;
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bo->buf_handle = buf_handle;
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bo->va_handle = va_handle;
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bo->gpu_va = vmc_addr;
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bo->size = size;
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return 0;
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error_va_map:
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amdgpu_bo_va_op(buf_handle, 0,
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size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
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error_va_alloc:
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amdgpu_va_range_free(va_handle);
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error_bo_alloc:
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amdgpu_bo_free(buf_handle);
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return r;
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}
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static int import_dma_buf_to_bo(amdgpu_device_handle dev,
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int dmabuf_fd, struct amdgpu_cp_dma_bo *bo) {
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amdgpu_va_handle va_handle;
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uint64_t vmc_addr;
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int r;
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struct amdgpu_bo_import_result bo_import_result = {};
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r = amdgpu_bo_import(dev, amdgpu_bo_handle_type_dma_buf_fd,
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dmabuf_fd, &bo_import_result);
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if (r)
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goto error_bo_import;
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r = amdgpu_va_range_alloc(dev, amdgpu_gpu_va_range_general,
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bo_import_result.alloc_size, 0, 0,
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&vmc_addr, &va_handle, 0);
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if (r)
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goto error_va_alloc;
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r = amdgpu_bo_va_op(bo_import_result.buf_handle, 0,
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bo_import_result.alloc_size, vmc_addr,
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AMDGPU_VM_PAGE_READABLE |
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AMDGPU_VM_PAGE_WRITEABLE |
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AMDGPU_VM_PAGE_EXECUTABLE,
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AMDGPU_VA_OP_MAP);
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if (r)
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goto error_va_map;
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bo->buf_handle = bo_import_result.buf_handle;
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bo->va_handle = va_handle;
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bo->gpu_va = vmc_addr;
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bo->size = bo_import_result.alloc_size;
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return 0;
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error_va_map:
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amdgpu_bo_va_op(bo_import_result.buf_handle, 0,
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bo_import_result.alloc_size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
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error_va_alloc:
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amdgpu_va_range_free(va_handle);
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error_bo_import:
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amdgpu_bo_free(bo_import_result.buf_handle);
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return r;
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}
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static int free_bo(struct amdgpu_cp_dma_bo bo) {
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int r;
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r = amdgpu_bo_va_op(bo.buf_handle, 0,
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bo.size, bo.gpu_va, 0, AMDGPU_VA_OP_UNMAP);
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if(r)
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return r;
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r = amdgpu_va_range_free(bo.va_handle);
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if(r)
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return r;
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r = amdgpu_bo_free(bo.buf_handle);
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if(r)
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return r;
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return 0;
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}
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static int submit_and_sync() {
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struct amdgpu_cs_request ibs_request = {0};
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struct amdgpu_cs_ib_info ib_info = {0};
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struct amdgpu_cs_fence fence_status = {0};
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uint32_t expired;
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uint32_t family_id, chip_id, chip_rev;
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unsigned gc_ip_type;
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int r;
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r = amdgpu_bo_list_create(executing_device_handle,
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num_resources, resources,
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NULL, &ibs_request.resources);
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if (r)
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return r;
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family_id = executing_device_handle->info.family_id;
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chip_id = executing_device_handle->info.chip_external_rev;
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chip_rev = executing_device_handle->info.chip_rev;
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gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ?
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AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX;
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ib_info.ib_mc_address = ib_mc_address;
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ib_info.size = num_dword;
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ibs_request.ip_type = gc_ip_type;
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ibs_request.number_of_ibs = 1;
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ibs_request.ibs = &ib_info;
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ibs_request.fence_info.handle = NULL;
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r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
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if (r)
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return r;
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r = amdgpu_bo_list_destroy(ibs_request.resources);
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if (r)
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return r;
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fence_status.context = context_handle;
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fence_status.ip_type = gc_ip_type;
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fence_status.fence = ibs_request.seq_no;
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r = amdgpu_cs_query_fence_status(&fence_status,
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AMDGPU_TIMEOUT_INFINITE,
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0, &expired);
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if (r)
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return r;
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return 0;
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}
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static void cp_dma_cmd(struct amdgpu_cp_dma_bo src_bo,
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struct amdgpu_cp_dma_bo dst_bo) {
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_Static_assert(DMA_SIZE < (1 << 26), "DMA size exceeds CP DMA maximium!");
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ib_cpu[0] = 0xc0055000;
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ib_cpu[1] = 0x80000000;
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ib_cpu[2] = src_bo.gpu_va & 0x00000000ffffffff;
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ib_cpu[3] = (src_bo.gpu_va & 0xffffffff00000000) >> 32;
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ib_cpu[4] = dst_bo.gpu_va & 0x00000000ffffffff;
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ib_cpu[5] = (dst_bo.gpu_va & 0xffffffff00000000) >> 32;
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// size is read from the lower 26bits.
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ib_cpu[6] = ((1 << 26) - 1) & DMA_SIZE;
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ib_cpu[7] = 0xffff1000;
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num_dword = 8;
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resources[0] = src_bo.buf_handle;
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resources[1] = dst_bo.buf_handle;
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resources[2] = ib_handle;
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num_resources = 3;
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}
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static void amdgpu_cp_dma(uint32_t src_heap, uint32_t dst_heap) {
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int r;
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struct amdgpu_cp_dma_bo src_bo = {0};
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struct amdgpu_cp_dma_bo dst_bo = {0};
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void *src_bo_cpu;
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void *dst_bo_cpu;
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/* allocate the src bo, set its data to DMA_DATA_BYTE */
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r = allocate_bo_and_va(executing_device_handle, DMA_SIZE, 4096,
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src_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &src_bo);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_cpu_map(src_bo.buf_handle, (void **)&src_bo_cpu);
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CU_ASSERT_EQUAL(r, 0);
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memset(src_bo_cpu, DMA_DATA_BYTE, DMA_SIZE);
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r = amdgpu_bo_cpu_unmap(src_bo.buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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/* allocate the dst bo and clear its content to all 0 */
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r = allocate_bo_and_va(executing_device_handle, DMA_SIZE, 4096,
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dst_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &dst_bo);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_cpu_map(dst_bo.buf_handle, (void **)&dst_bo_cpu);
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CU_ASSERT_EQUAL(r, 0);
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_Static_assert(DMA_DATA_BYTE != 0, "Initialization data should be different from DMA data!");
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memset(dst_bo_cpu, 0, DMA_SIZE);
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/* record CP DMA command and dispatch the command */
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cp_dma_cmd(src_bo, dst_bo);
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r = submit_and_sync();
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CU_ASSERT_EQUAL(r, 0);
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/* verify the dst bo is filled with DMA_DATA_BYTE */
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CU_ASSERT_EQUAL(memcmp(dst_bo_cpu, reference_data, DMA_SIZE) == 0, true);
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r = amdgpu_bo_cpu_unmap(dst_bo.buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = free_bo(src_bo);
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CU_ASSERT_EQUAL(r, 0);
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r = free_bo(dst_bo);
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CU_ASSERT_EQUAL(r, 0);
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}
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static void amdgpu_cp_dma_p2p(uint32_t src_heap, uint32_t dst_heap) {
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int r;
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struct amdgpu_cp_dma_bo exported_bo = {0};
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int dma_buf_fd;
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int dma_buf_fd_dup;
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struct amdgpu_cp_dma_bo src_bo = {0};
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struct amdgpu_cp_dma_bo imported_dst_bo = {0};
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void *exported_bo_cpu;
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void *src_bo_cpu;
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/* allocate a bo on the peer device and export it to dma-buf */
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r = allocate_bo_and_va(peer_exporting_device_handle, DMA_SIZE, 4096,
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src_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &exported_bo);
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CU_ASSERT_EQUAL(r, 0);
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/* map the exported bo and clear its content to 0 */
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_Static_assert(DMA_DATA_BYTE != 0, "Initialization data should be different from DMA data!");
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r = amdgpu_bo_cpu_map(exported_bo.buf_handle, (void **)&exported_bo_cpu);
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CU_ASSERT_EQUAL(r, 0);
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memset(exported_bo_cpu, 0, DMA_SIZE);
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r = amdgpu_bo_export(exported_bo.buf_handle,
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amdgpu_bo_handle_type_dma_buf_fd, (uint32_t*)&dma_buf_fd);
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CU_ASSERT_EQUAL(r, 0);
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// According to amdgpu_drm:
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// "Buffer must be "imported" only using new "fd"
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// (different from one used by "exporter")"
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dma_buf_fd_dup = dup(dma_buf_fd);
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r = close(dma_buf_fd);
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CU_ASSERT_EQUAL(r, 0);
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/* import the dma-buf to the executing device, imported bo is the DMA destination */
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r = import_dma_buf_to_bo(
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executing_device_handle, dma_buf_fd_dup, &imported_dst_bo);
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CU_ASSERT_EQUAL(r, 0);
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r = close(dma_buf_fd_dup);
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CU_ASSERT_EQUAL(r, 0);
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/* allocate the src bo and set its content to DMA_DATA_BYTE */
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r = allocate_bo_and_va(executing_device_handle, DMA_SIZE, 4096,
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dst_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &src_bo);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_cpu_map(src_bo.buf_handle, (void **)&src_bo_cpu);
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CU_ASSERT_EQUAL(r, 0);
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memset(src_bo_cpu, DMA_DATA_BYTE, DMA_SIZE);
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r = amdgpu_bo_cpu_unmap(src_bo.buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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/* record CP DMA command and dispatch the command */
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cp_dma_cmd(src_bo, imported_dst_bo);
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r = submit_and_sync();
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CU_ASSERT_EQUAL(r, 0);
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/* verify the bo from the peer device is filled with DMA_DATA_BYTE */
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CU_ASSERT_EQUAL(memcmp(exported_bo_cpu, reference_data, DMA_SIZE) == 0, true);
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r = amdgpu_bo_cpu_unmap(exported_bo.buf_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = free_bo(exported_bo);
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CU_ASSERT_EQUAL(r, 0);
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r = free_bo(imported_dst_bo);
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CU_ASSERT_EQUAL(r, 0);
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r = free_bo(src_bo);
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CU_ASSERT_EQUAL(r, 0);
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}
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static void amdgpu_cp_dma_host_to_vram(void) {
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amdgpu_cp_dma(AMDGPU_GEM_DOMAIN_GTT, AMDGPU_GEM_DOMAIN_VRAM);
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}
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static void amdgpu_cp_dma_vram_to_host(void) {
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amdgpu_cp_dma(AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_DOMAIN_GTT);
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}
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static void amdgpu_cp_dma_p2p_vram_to_vram(void) {
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amdgpu_cp_dma_p2p(AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_DOMAIN_VRAM);
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}
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static void amdgpu_cp_dma_p2p_host_to_vram(void) {
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amdgpu_cp_dma_p2p(AMDGPU_GEM_DOMAIN_GTT, AMDGPU_GEM_DOMAIN_VRAM);
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}
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static void amdgpu_cp_dma_p2p_vram_to_host(void) {
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amdgpu_cp_dma_p2p(AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_DOMAIN_GTT);
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}
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int suite_cp_dma_tests_init() {
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int r;
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r = amdgpu_device_initialize(drm_amdgpu[0],
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&executing_device_major_version,
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&executing_device_minor_version,
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&executing_device_handle);
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if (r)
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return CUE_SINIT_FAILED;
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r = amdgpu_cs_ctx_create(executing_device_handle, &context_handle);
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if (r)
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return CUE_SINIT_FAILED;
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r = amdgpu_bo_alloc_and_map(executing_device_handle, IB_SIZE, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&ib_handle, (void**)&ib_cpu,
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&ib_mc_address, &ib_va_handle);
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if (r)
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return CUE_SINIT_FAILED;
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if (do_p2p) {
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r = amdgpu_device_initialize(drm_amdgpu[1],
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&peer_exporting_device_major_version,
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&peer_exporting_device_minor_version,
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&peer_exporting_device_handle);
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if (r)
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return CUE_SINIT_FAILED;
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}
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reference_data = (uint8_t*)malloc(DMA_SIZE);
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if (!reference_data)
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return CUE_SINIT_FAILED;
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memset(reference_data, DMA_DATA_BYTE, DMA_SIZE);
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return CUE_SUCCESS;
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}
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int suite_cp_dma_tests_clean() {
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int r;
|
|
|
|
free(reference_data);
|
|
|
|
r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
|
|
ib_mc_address, IB_SIZE);
|
|
if (r)
|
|
return CUE_SCLEAN_FAILED;
|
|
|
|
r = amdgpu_cs_ctx_free(context_handle);
|
|
if (r)
|
|
return CUE_SCLEAN_FAILED;
|
|
|
|
r = amdgpu_device_deinitialize(executing_device_handle);
|
|
if (r)
|
|
return CUE_SCLEAN_FAILED;
|
|
|
|
if (do_p2p) {
|
|
r = amdgpu_device_deinitialize(peer_exporting_device_handle);
|
|
if (r)
|
|
return CUE_SCLEAN_FAILED;
|
|
}
|
|
|
|
return CUE_SUCCESS;
|
|
}
|
|
|
|
CU_BOOL suite_cp_dma_tests_enable(void) {
|
|
int r = 0;
|
|
|
|
if (amdgpu_device_initialize(drm_amdgpu[0],
|
|
&executing_device_major_version,
|
|
&executing_device_minor_version,
|
|
&executing_device_handle))
|
|
return CU_FALSE;
|
|
|
|
if (!(executing_device_handle->info.family_id >= AMDGPU_FAMILY_AI &&
|
|
executing_device_handle->info.family_id <= AMDGPU_FAMILY_NV)) {
|
|
printf("Testing device has ASIC that is not supported by CP-DMA test suite!\n");
|
|
return CU_FALSE;
|
|
}
|
|
|
|
if (amdgpu_device_deinitialize(executing_device_handle))
|
|
return CU_FALSE;
|
|
|
|
if (drm_amdgpu[1] >= 0) {
|
|
r = amdgpu_device_initialize(drm_amdgpu[1],
|
|
&peer_exporting_device_major_version,
|
|
&peer_exporting_device_minor_version,
|
|
&peer_exporting_device_handle);
|
|
|
|
if (r == 0 && (peer_exporting_device_handle->info.family_id >= AMDGPU_FAMILY_AI &&
|
|
peer_exporting_device_handle->info.family_id <= AMDGPU_FAMILY_NV)) {
|
|
do_p2p = true;
|
|
}
|
|
|
|
if (r == 0 && amdgpu_device_deinitialize(peer_exporting_device_handle) != 0) {
|
|
printf("Deinitialize peer_exporting_device_handle failed!\n");
|
|
return CU_FALSE;
|
|
}
|
|
}
|
|
|
|
if (!do_p2p) {
|
|
amdgpu_set_test_active("CP DMA Tests", "Peer to Peer CP DMA write VRAM to VRAM", CU_FALSE);
|
|
amdgpu_set_test_active("CP DMA Tests", "Peer to Peer CP DMA write Host to VRAM", CU_FALSE);
|
|
amdgpu_set_test_active("CP DMA Tests", "Peer to Peer CP DMA write VRAM to Host", CU_FALSE);
|
|
printf("Peer device is not opened or has ASIC not supported by the suite, skip all Peer to Peer tests.\n");
|
|
}
|
|
|
|
return CU_TRUE;
|
|
}
|