235 lines
7.3 KiB
C
235 lines
7.3 KiB
C
/*
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* Copyright 2007 Stephane Marchesin
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drm.h"
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#include "nouveau_drv.h"
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struct reg_interval
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{
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uint32_t reg;
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int number;
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} nv04_graph_ctx_regs [] = {
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{NV04_PGRAPH_CTX_SWITCH1, 1},
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{NV04_PGRAPH_CTX_SWITCH2, 1},
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{NV04_PGRAPH_CTX_SWITCH3, 1},
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{NV04_PGRAPH_CTX_SWITCH4, 1},
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{NV04_PGRAPH_CTX_USER, 1},
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{NV04_PGRAPH_CTX_CACHE1, 8},
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{NV04_PGRAPH_CTX_CACHE2, 8},
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{NV04_PGRAPH_CTX_CACHE3, 8},
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{NV04_PGRAPH_CTX_CACHE4, 8},
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{NV03_PGRAPH_ABS_X_RAM, 32},
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{NV03_PGRAPH_ABS_Y_RAM, 32},
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{NV03_PGRAPH_X_MISC, 1},
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{NV03_PGRAPH_Y_MISC, 1},
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{NV04_PGRAPH_VALID1, 1},
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{NV04_PGRAPH_SOURCE_COLOR, 1},
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{NV04_PGRAPH_MISC24_0, 1},
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{NV03_PGRAPH_XY_LOGIC_MISC0, 1},
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{NV03_PGRAPH_XY_LOGIC_MISC1, 1},
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{NV03_PGRAPH_XY_LOGIC_MISC2, 1},
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{NV03_PGRAPH_XY_LOGIC_MISC3, 1},
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{NV03_PGRAPH_CLIPX_0, 1},
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{NV03_PGRAPH_CLIPX_1, 1},
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{NV03_PGRAPH_CLIPY_0, 1},
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{NV03_PGRAPH_CLIPY_1, 1},
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{NV03_PGRAPH_ABS_ICLIP_XMAX, 1},
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{NV03_PGRAPH_ABS_ICLIP_YMAX, 1},
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{NV03_PGRAPH_ABS_UCLIP_XMIN, 1},
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{NV03_PGRAPH_ABS_UCLIP_YMIN, 1},
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{NV03_PGRAPH_ABS_UCLIP_XMAX, 1},
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{NV03_PGRAPH_ABS_UCLIP_YMAX, 1},
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{NV03_PGRAPH_ABS_UCLIPA_XMIN, 1},
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{NV03_PGRAPH_ABS_UCLIPA_YMIN, 1},
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{NV03_PGRAPH_ABS_UCLIPA_XMAX, 1},
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{NV03_PGRAPH_ABS_UCLIPA_YMAX, 1},
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{NV04_PGRAPH_MISC24_1, 1},
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{NV04_PGRAPH_MISC24_2, 1},
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{NV04_PGRAPH_VALID2, 1},
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{NV04_PGRAPH_PASSTHRU_0, 1},
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{NV04_PGRAPH_PASSTHRU_1, 1},
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{NV04_PGRAPH_PASSTHRU_2, 1},
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{NV04_PGRAPH_COMBINE_0_ALPHA, 1},
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{NV04_PGRAPH_COMBINE_0_COLOR, 1},
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{NV04_PGRAPH_COMBINE_1_ALPHA, 1},
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{NV04_PGRAPH_COMBINE_1_COLOR, 1},
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// texture state
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{NV04_PGRAPH_FORMAT_0, 1},
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{NV04_PGRAPH_FORMAT_1, 1},
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{NV04_PGRAPH_FILTER_0, 1},
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{NV04_PGRAPH_FILTER_1, 1},
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// vertex state
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{0x004005c0, 1},
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{0x004005c4, 1},
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{0x004005c8, 1},
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{0x004005cc, 1},
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{0x004005d0, 1},
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{0x004005d4, 1},
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{0x004005d8, 1},
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{0x004005dc, 1},
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{0x004005e0, 1},
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{NV03_PGRAPH_MONO_COLOR0, 1},
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{NV04_PGRAPH_ROP3, 1},
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{NV04_PGRAPH_BETA_AND, 1},
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{NV04_PGRAPH_BETA_PREMULT, 1},
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{NV04_PGRAPH_FORMATS, 1},
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{NV04_PGRAPH_BOFFSET0, 6},
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{NV04_PGRAPH_BBASE0, 6},
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{NV04_PGRAPH_BPITCH0, 5},
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{NV04_PGRAPH_BLIMIT0, 6},
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{NV04_PGRAPH_BSWIZZLE2, 1},
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{NV04_PGRAPH_BSWIZZLE5, 1},
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{NV04_PGRAPH_SURFACE, 1},
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{NV04_PGRAPH_STATE, 1},
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{NV04_PGRAPH_NOTIFY, 1},
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{NV04_PGRAPH_BPIXEL, 1},
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{NV04_PGRAPH_DMA_PITCH, 1},
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{NV04_PGRAPH_DVD_COLORFMT, 1},
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{NV04_PGRAPH_SCALED_FORMAT, 1},
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{NV04_PGRAPH_PATT_COLOR0, 1},
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{NV04_PGRAPH_PATT_COLOR1, 1},
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{NV04_PGRAPH_PATTERN, 2},
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{NV04_PGRAPH_PATTERN_SHAPE, 1},
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{NV04_PGRAPH_CHROMA, 1},
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{NV04_PGRAPH_CONTROL0, 1},
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{NV04_PGRAPH_CONTROL1, 1},
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{NV04_PGRAPH_CONTROL2, 1},
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{NV04_PGRAPH_BLEND, 1},
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{NV04_PGRAPH_STORED_FMT, 1},
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{NV04_PGRAPH_PATT_COLORRAM, 64},
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{NV04_PGRAPH_U_RAM, 16},
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{NV04_PGRAPH_V_RAM, 16},
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{NV04_PGRAPH_W_RAM, 16},
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{NV04_PGRAPH_DMA_START_0, 1},
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{NV04_PGRAPH_DMA_START_1, 1},
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{NV04_PGRAPH_DMA_LENGTH, 1},
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{NV04_PGRAPH_DMA_MISC, 1},
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{NV04_PGRAPH_DMA_DATA_0, 1},
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{NV04_PGRAPH_DMA_DATA_1, 1},
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{NV04_PGRAPH_DMA_RM, 1},
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{NV04_PGRAPH_DMA_A_XLATE_INST, 1},
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{NV04_PGRAPH_DMA_A_CONTROL, 1},
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{NV04_PGRAPH_DMA_A_LIMIT, 1},
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{NV04_PGRAPH_DMA_A_TLB_PTE, 1},
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{NV04_PGRAPH_DMA_A_TLB_TAG, 1},
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{NV04_PGRAPH_DMA_A_ADJ_OFFSET, 1},
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{NV04_PGRAPH_DMA_A_OFFSET, 1},
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{NV04_PGRAPH_DMA_A_SIZE, 1},
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{NV04_PGRAPH_DMA_A_Y_SIZE, 1},
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{NV04_PGRAPH_DMA_B_XLATE_INST, 1},
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{NV04_PGRAPH_DMA_B_CONTROL, 1},
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{NV04_PGRAPH_DMA_B_LIMIT, 1},
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{NV04_PGRAPH_DMA_B_TLB_PTE, 1},
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{NV04_PGRAPH_DMA_B_TLB_TAG, 1},
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{NV04_PGRAPH_DMA_B_ADJ_OFFSET, 1},
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{NV04_PGRAPH_DMA_B_OFFSET, 1},
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{NV04_PGRAPH_DMA_B_SIZE, 1},
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{NV04_PGRAPH_DMA_B_Y_SIZE, 1},
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};
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void nouveau_nv04_context_switch(drm_device_t *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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int channel, channel_old, i, j, index;
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channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
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channel_old = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
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DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
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NV_WRITE(NV03_PFIFO_CACHES, 0x0);
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NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
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NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0);
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NV_WRITE(NV04_PGRAPH_FIFO,0x0);
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// save PGRAPH context
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index=0;
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for (i = 0; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
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for (j = 0; j<nv04_graph_ctx_regs[i].number; j++)
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{
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dev_priv->fifos[channel_old].pgraph_ctx[index] = NV_READ(nv04_graph_ctx_regs[i].reg+j*4);
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index++;
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}
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nouveau_wait_for_idle(dev);
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NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000);
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NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24));
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nouveau_wait_for_idle(dev);
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// restore PGRAPH context
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//XXX not working yet
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#if 1
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index=0;
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for (i = 0; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
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for (j = 0; j<nv04_graph_ctx_regs[i].number; j++)
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{
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NV_WRITE(nv04_graph_ctx_regs[i].reg+j*4, dev_priv->fifos[channel].pgraph_ctx[index]);
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index++;
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}
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nouveau_wait_for_idle(dev);
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#endif
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NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
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NV_WRITE(NV04_PGRAPH_CTX_USER, channel << 24);
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NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
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NV_WRITE(NV04_PGRAPH_FIFO,0x0);
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NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
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NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1);
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NV_WRITE(NV03_PFIFO_CACHES, 0x1);
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NV_WRITE(NV04_PGRAPH_FIFO,0x1);
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}
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int nv04_graph_context_create(drm_device_t *dev, int channel) {
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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DRM_DEBUG("nv04_graph_context_create %d\n", channel);
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memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx));
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//dev_priv->fifos[channel].pgraph_ctx_user = channel << 24;
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dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff;
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/* is it really needed ??? */
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//dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4);
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//dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0);
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return 0;
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}
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int nv04_graph_init(drm_device_t *dev) {
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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// check the context is big enough
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int i,sum=0;
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for ( i = 0 ; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
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sum+=nv04_graph_ctx_regs[i].number;
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if ( sum*4>sizeof(dev_priv->fifos[0].pgraph_ctx) )
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DRM_ERROR("pgraph_ctx too small\n");
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return 0;
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}
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