321 lines
9.4 KiB
C
321 lines
9.4 KiB
C
/*
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* Copyright 2008 Jérôme Glisse
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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*/
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#include "radeon_ms.h"
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#include "amd.h"
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#define RADEON_DST_Y_X 0x1438
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#define RADEON_SRC_Y_X 0x1434
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#define RADEON_DP_CNTL 0x16c0
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#define RADEON_DP_GUI_MASTER_CNTL 0x146c
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#define RADEON_DP_BRUSH_BKGD_CLR 0x1478
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#define RADEON_DP_BRUSH_FRGD_CLR 0x147c
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#define RADEON_DP_WRITE_MASK 0x16cc
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#define RADEON_DST_PITCH_OFFSET 0x142c
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#define RADEON_SRC_PITCH_OFFSET 0x1428
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#define RADEON_DST_HEIGHT_WIDTH 0x143c
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struct legacy_check
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{
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/* for 2D operations */
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uint32_t dp_gui_master_cntl;
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uint32_t dst_offset;
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uint32_t dst_pitch;
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struct amd_cmd_bo *dst;
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uint32_t dst_x;
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uint32_t dst_y;
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uint32_t dst_h;
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uint32_t dst_w;
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struct amd_cmd_bo *src;
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uint32_t src_pitch;
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uint32_t src_x;
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uint32_t src_y;
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};
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static int check_blit(struct drm_device *dev, struct amd_cmd *cmd)
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{
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struct legacy_check *legacy_check;
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long bpp, start, end;
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legacy_check = (struct legacy_check *)cmd->driver;
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/* check that gui master cntl have been set */
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if (legacy_check->dp_gui_master_cntl == 0xffffffff) {
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return -EINVAL;
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}
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switch ((legacy_check->dp_gui_master_cntl >> 8) & 0xf) {
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case 2:
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bpp = 1;
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break;
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case 3:
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case 4:
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bpp = 2;
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break;
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case 6:
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bpp = 4;
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break;
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default:
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return -EINVAL;
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}
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/* check that a destination have been set */
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if (legacy_check->dst == (void *)-1) {
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return -EINVAL;
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}
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if (legacy_check->dst_pitch == 0xffffffff) {
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return -EINVAL;
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}
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if (legacy_check->dst_x == 0xffffffff) {
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return -EINVAL;
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}
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if (legacy_check->dst_y == 0xffffffff) {
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return -EINVAL;
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}
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if (legacy_check->dst_w == 0xffffffff) {
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return -EINVAL;
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}
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if (legacy_check->dst_h == 0xffffffff) {
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return -EINVAL;
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}
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/* compute start offset of blit */
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start = legacy_check->dst_pitch * legacy_check->dst_y +
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legacy_check->dst_x * bpp;
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/* compute end offset of blit */
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end = legacy_check->dst_pitch * legacy_check->dst_h +
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legacy_check->dst_w * bpp;
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/* FIXME: check that end offset is inside dst bo */
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/* check that a destination have been set */
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if (legacy_check->dp_gui_master_cntl & 1) {
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if (legacy_check->src == (void *)-1) {
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return -EINVAL;
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}
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if (legacy_check->src_pitch == 0xffffffff) {
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return -EINVAL;
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}
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if (legacy_check->src_x == 0xffffffff) {
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return -EINVAL;
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}
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if (legacy_check->src_y == 0xffffffff) {
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return -EINVAL;
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}
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/* compute start offset of blit */
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start = legacy_check->src_pitch * legacy_check->src_y +
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legacy_check->src_x * bpp;
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/* compute end offset of blit */
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end = legacy_check->src_pitch * legacy_check->dst_h +
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legacy_check->dst_w * bpp + start;
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/* FIXME: check that end offset is inside src bo */
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}
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return 0;
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}
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static int p0_dp_gui_master_cntl(struct drm_device *dev,
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struct amd_cmd *cmd,
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int cdw_id, int reg)
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{
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struct legacy_check *legacy_check;
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legacy_check = (struct legacy_check *)cmd->driver;
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legacy_check->dp_gui_master_cntl = cmd->cdw[cdw_id];
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/* we only accept src data type to be same as dst */
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if (((legacy_check->dp_gui_master_cntl >> 12) & 0x3) != 3) {
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return -EINVAL;
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}
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return 0;
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}
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static int p0_dst_pitch_offset(struct drm_device *dev,
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struct amd_cmd *cmd,
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int cdw_id, int reg)
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{
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struct legacy_check *legacy_check;
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uint32_t tmp;
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int ret;
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legacy_check = (struct legacy_check *)cmd->driver;
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legacy_check->dst_pitch = ((cmd->cdw[cdw_id] >> 22) & 0xff) << 6;
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tmp = cmd->cdw[cdw_id] & 0x003fffff;
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legacy_check->dst = amd_cmd_get_bo(cmd, tmp);
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if (legacy_check->dst == NULL) {
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DRM_ERROR("invalid bo (%d) for DST_PITCH_OFFSET register.\n",
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tmp);
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return -EINVAL;
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}
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ret = radeon_ms_bo_get_gpu_addr(dev, &legacy_check->dst->bo->mem, &tmp);
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if (ret) {
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DRM_ERROR("failed to get GPU offset for bo 0x%x.\n",
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legacy_check->dst->handle);
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return -EINVAL;
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}
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if (tmp & 0x3fff) {
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DRM_ERROR("bo 0x%x offset doesn't meet alignement 0x%x.\n",
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legacy_check->dst->handle, tmp);
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}
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cmd->cdw[cdw_id] &= 0xffc00000;
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cmd->cdw[cdw_id] |= (tmp >> 10);
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return 0;
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}
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static int p0_src_pitch_offset(struct drm_device *dev,
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struct amd_cmd *cmd,
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int cdw_id, int reg)
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{
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struct legacy_check *legacy_check;
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uint32_t tmp;
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int ret;
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legacy_check = (struct legacy_check *)cmd->driver;
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legacy_check->src_pitch = ((cmd->cdw[cdw_id] >> 22) & 0xff) << 6;
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tmp = cmd->cdw[cdw_id] & 0x003fffff;
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legacy_check->src = amd_cmd_get_bo(cmd, tmp);
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if (legacy_check->src == NULL) {
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DRM_ERROR("invalid bo (%d) for SRC_PITCH_OFFSET register.\n",
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tmp);
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return -EINVAL;
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}
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ret = radeon_ms_bo_get_gpu_addr(dev, &legacy_check->src->bo->mem, &tmp);
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if (ret) {
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DRM_ERROR("failed to get GPU offset for bo 0x%x.\n",
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legacy_check->src->handle);
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return -EINVAL;
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}
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if (tmp & 0x3fff) {
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DRM_ERROR("bo 0x%x offset doesn't meet alignement 0x%x.\n",
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legacy_check->src->handle, tmp);
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}
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cmd->cdw[cdw_id] &= 0xffc00000;
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cmd->cdw[cdw_id] |= (tmp >> 10);
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return 0;
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}
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static int p0_dst_y_x(struct drm_device *dev,
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struct amd_cmd *cmd,
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int cdw_id, int reg)
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{
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struct legacy_check *legacy_check;
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legacy_check = (struct legacy_check *)cmd->driver;
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legacy_check->dst_x = cmd->cdw[cdw_id] & 0xffff;
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legacy_check->dst_y = (cmd->cdw[cdw_id] >> 16) & 0xffff;
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return 0;
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}
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static int p0_src_y_x(struct drm_device *dev,
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struct amd_cmd *cmd,
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int cdw_id, int reg)
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{
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struct legacy_check *legacy_check;
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legacy_check = (struct legacy_check *)cmd->driver;
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legacy_check->src_x = cmd->cdw[cdw_id] & 0xffff;
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legacy_check->src_y = (cmd->cdw[cdw_id] >> 16) & 0xffff;
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return 0;
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}
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static int p0_dst_h_w(struct drm_device *dev,
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struct amd_cmd *cmd,
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int cdw_id, int reg)
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{
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struct legacy_check *legacy_check;
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legacy_check = (struct legacy_check *)cmd->driver;
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legacy_check->dst_w = cmd->cdw[cdw_id] & 0xffff;
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legacy_check->dst_h = (cmd->cdw[cdw_id] >> 16) & 0xffff;
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return check_blit(dev, cmd);
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}
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static int legacy_cmd_check(struct drm_device *dev,
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struct amd_cmd *cmd)
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{
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struct legacy_check legacy_check;
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memset(&legacy_check, 0xff, sizeof(struct legacy_check));
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cmd->driver = &legacy_check;
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return amd_cmd_check(dev, cmd);
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}
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int amd_legacy_cmd_module_destroy(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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dev_priv->cmd_module.check = NULL;
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if (dev_priv->cmd_module.numof_p0_checkers) {
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drm_free(dev_priv->cmd_module.check_p0,
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dev_priv->cmd_module.numof_p0_checkers *
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sizeof(void*), DRM_MEM_DRIVER);
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dev_priv->cmd_module.numof_p0_checkers = 0;
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}
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if (dev_priv->cmd_module.numof_p3_checkers) {
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drm_free(dev_priv->cmd_module.check_p3,
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dev_priv->cmd_module.numof_p3_checkers *
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sizeof(void*), DRM_MEM_DRIVER);
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dev_priv->cmd_module.numof_p3_checkers = 0;
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}
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return 0;
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}
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int amd_legacy_cmd_module_initialize(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct amd_cmd_module *checker = &dev_priv->cmd_module;
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long size;
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/* packet 0 */
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checker->numof_p0_checkers = 0x5000 >> 2;
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size = checker->numof_p0_checkers * sizeof(void*);
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checker->check_p0 = drm_alloc(size, DRM_MEM_DRIVER);
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if (checker->check_p0 == NULL) {
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amd_legacy_cmd_module_destroy(dev);
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return -ENOMEM;
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}
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/* initialize to -1 */
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memset(checker->check_p0, 0xff, size);
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/* packet 3 */
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checker->numof_p3_checkers = 20;
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size = checker->numof_p3_checkers * sizeof(void*);
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checker->check_p3 = drm_alloc(size, DRM_MEM_DRIVER);
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if (checker->check_p3 == NULL) {
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amd_legacy_cmd_module_destroy(dev);
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return -ENOMEM;
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}
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/* initialize to -1 */
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memset(checker->check_p3, 0xff, size);
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/* initialize packet0 checker */
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checker->check_p0[RADEON_DST_Y_X >> 2] = p0_dst_y_x;
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checker->check_p0[RADEON_SRC_Y_X >> 2] = p0_src_y_x;
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checker->check_p0[RADEON_DST_HEIGHT_WIDTH >> 2] = p0_dst_h_w;
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checker->check_p0[RADEON_DST_PITCH_OFFSET >> 2] = p0_dst_pitch_offset;
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checker->check_p0[RADEON_SRC_PITCH_OFFSET >> 2] = p0_src_pitch_offset;
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checker->check_p0[RADEON_DP_GUI_MASTER_CNTL>>2] = p0_dp_gui_master_cntl;
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checker->check_p0[RADEON_DP_BRUSH_FRGD_CLR >> 2] = NULL;
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checker->check_p0[RADEON_DP_WRITE_MASK >> 2] = NULL;
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checker->check_p0[RADEON_DP_CNTL >> 2] = NULL;
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checker->check = legacy_cmd_check;
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return 0;
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}
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