477 lines
10 KiB
C
477 lines
10 KiB
C
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/****************************************************************************
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* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
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* *
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* All Rights Reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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* *
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
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* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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***************************************************************************/
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#include "xgi_drv.h"
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#include "xgi_regs.h"
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int xgi_ge_reset_ioctl(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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struct xgi_info *info = dev->dev_private;
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xgi_disable_ge(info);
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xgi_enable_ge(info);
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return 0;
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}
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/*
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* irq functions
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*/
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#define STALL_INTERRUPT_RESET_THRESHOLD 0xffff
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static unsigned int s_invalid_begin = 0;
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static bool xgi_validate_signal(volatile u8 *mmio_vbase)
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{
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volatile u32 *const ge_3d_status =
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(volatile u32 *)(mmio_vbase + 0x2800);
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const u32 old_ge_status = ge_3d_status[0x00];
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if (old_ge_status & 0x001c0000) {
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u16 check;
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/* Check Read back status */
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*(mmio_vbase + 0x235c) = 0x80;
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check = *((volatile u16 *)(mmio_vbase + 0x2360));
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if ((check & 0x3f) != ((check & 0x3f00) >> 8)) {
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return FALSE;
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}
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/* Check RO channel */
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*(mmio_vbase + 0x235c) = 0x83;
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check = *((volatile u16 *)(mmio_vbase + 0x2360));
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if ((check & 0x0f) != ((check & 0xf0) >> 4)) {
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return FALSE;
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}
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/* Check RW channel */
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*(mmio_vbase + 0x235c) = 0x88;
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check = *((volatile u16 *)(mmio_vbase + 0x2360));
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if ((check & 0x0f) != ((check & 0xf0) >> 4)) {
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return FALSE;
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}
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/* Check RO channel outstanding */
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*(mmio_vbase + 0x235c) = 0x8f;
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check = *((volatile u16 *)(mmio_vbase + 0x2360));
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if (0 != (check & 0x3ff)) {
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return FALSE;
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}
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/* Check RW channel outstanding */
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*(mmio_vbase + 0x235c) = 0x90;
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check = *((volatile u16 *)(mmio_vbase + 0x2360));
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if (0 != (check & 0x3ff)) {
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return FALSE;
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}
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/* No pending PCIE request. GE stall. */
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}
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return TRUE;
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}
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static void xgi_ge_hang_reset(volatile u8 *mmio_vbase)
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{
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volatile u32 *const ge_3d_status =
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(volatile u32 *)(mmio_vbase + 0x2800);
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int time_out = 0xffff;
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*(mmio_vbase + 0xb057) = 8;
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while (0 != (ge_3d_status[0x00] & 0xf0000000)) {
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while (0 != ((--time_out) & 0xfff))
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/* empty */ ;
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if (0 == time_out) {
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u8 old_3ce;
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u8 old_3cf;
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u8 old_index;
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u8 old_36;
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DRM_INFO("Can not reset back 0x%x!\n",
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ge_3d_status[0x00]);
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*(mmio_vbase + 0xb057) = 0;
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/* Have to use 3x5.36 to reset. */
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/* Save and close dynamic gating */
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old_3ce = *(mmio_vbase + 0x3ce);
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*(mmio_vbase + 0x3ce) = 0x2a;
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old_3cf = *(mmio_vbase + 0x3cf);
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*(mmio_vbase + 0x3cf) = old_3cf & 0xfe;
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/* Reset GE */
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old_index = *(mmio_vbase + 0x3d4);
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*(mmio_vbase + 0x3d4) = 0x36;
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old_36 = *(mmio_vbase + 0x3d5);
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*(mmio_vbase + 0x3d5) = old_36 | 0x10;
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while (0 != ((--time_out) & 0xfff))
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/* empty */ ;
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*(mmio_vbase + 0x3d5) = old_36;
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*(mmio_vbase + 0x3d4) = old_index;
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/* Restore dynamic gating */
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*(mmio_vbase + 0x3cf) = old_3cf;
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*(mmio_vbase + 0x3ce) = old_3ce;
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break;
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}
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}
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*(mmio_vbase + 0xb057) = 0;
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}
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bool xgi_ge_irq_handler(struct xgi_info * info)
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{
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volatile u8 *const mmio_vbase = info->mmio_map->handle;
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volatile u32 *const ge_3d_status =
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(volatile u32 *)(mmio_vbase + 0x2800);
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const u32 int_status = ge_3d_status[4];
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bool is_support_auto_reset = FALSE;
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/* Check GE on/off */
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if (0 == (0xffffc0f0 & int_status)) {
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u32 old_pcie_cmd_fetch_Addr = ge_3d_status[0x0a];
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if (0 != (0x1000 & int_status)) {
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/* We got GE stall interrupt.
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*/
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ge_3d_status[0x04] = int_status | 0x04000000;
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if (is_support_auto_reset) {
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static cycles_t last_tick;
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static unsigned continue_int_count = 0;
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/* OE II is busy. */
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if (!xgi_validate_signal(mmio_vbase)) {
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/* Nothing but skip. */
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} else if (0 == continue_int_count++) {
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last_tick = get_cycles();
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} else {
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const cycles_t new_tick = get_cycles();
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if ((new_tick - last_tick) >
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STALL_INTERRUPT_RESET_THRESHOLD) {
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continue_int_count = 0;
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} else if (continue_int_count >= 3) {
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continue_int_count = 0;
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/* GE Hung up, need reset. */
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DRM_INFO("Reset GE!\n");
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xgi_ge_hang_reset(mmio_vbase);
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}
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}
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}
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} else if (0 != (0x1 & int_status)) {
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s_invalid_begin++;
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ge_3d_status[0x04] = (int_status & ~0x01) | 0x04000000;
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}
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return TRUE;
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}
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return FALSE;
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}
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bool xgi_crt_irq_handler(struct xgi_info * info)
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{
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bool ret = FALSE;
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u8 save_3ce = DRM_READ8(info->mmio_map, 0x3ce);
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if (IN3CFB(info->mmio_map, 0x37) & 0x01) // CRT1 interrupt just happened
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{
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u8 op3cf_3d;
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u8 op3cf_37;
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// What happened?
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op3cf_37 = IN3CFB(info->mmio_map, 0x37);
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// Clear CRT interrupt
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op3cf_3d = IN3CFB(info->mmio_map, 0x3d);
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OUT3CFB(info->mmio_map, 0x3d, (op3cf_3d | 0x04));
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OUT3CFB(info->mmio_map, 0x3d, (op3cf_3d & ~0x04));
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ret = TRUE;
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}
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DRM_WRITE8(info->mmio_map, 0x3ce, save_3ce);
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return (ret);
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}
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bool xgi_dvi_irq_handler(struct xgi_info * info)
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{
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bool ret = FALSE;
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const u8 save_3ce = DRM_READ8(info->mmio_map, 0x3ce);
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if (IN3CFB(info->mmio_map, 0x38) & 0x20) { // DVI interrupt just happened
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const u8 save_3x4 = DRM_READ8(info->mmio_map, 0x3d4);
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u8 op3cf_39;
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u8 op3cf_37;
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u8 op3x5_5a;
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// What happened?
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op3cf_37 = IN3CFB(info->mmio_map, 0x37);
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//Notify BIOS that DVI plug/unplug happened
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op3x5_5a = IN3X5B(info->mmio_map, 0x5a);
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OUT3X5B(info->mmio_map, 0x5a, op3x5_5a & 0xf7);
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DRM_WRITE8(info->mmio_map, 0x3d4, save_3x4);
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// Clear DVI interrupt
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op3cf_39 = IN3CFB(info->mmio_map, 0x39);
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OUT3C5B(info->mmio_map, 0x39, (op3cf_39 & ~0x01)); //Set 3cf.39 bit 0 to 0
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OUT3C5B(info->mmio_map, 0x39, (op3cf_39 | 0x01)); //Set 3cf.39 bit 0 to 1
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ret = TRUE;
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}
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DRM_WRITE8(info->mmio_map, 0x3ce, save_3ce);
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return (ret);
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}
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void xgi_dump_register(struct xgi_info * info)
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{
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int i, j;
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unsigned char temp;
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// 0x3C5
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printk("\r\n=====xgi_dump_register========0x%x===============\r\n",
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0x3C5);
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for (i = 0; i < 0x10; i++) {
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if (i == 0) {
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printk("%5x", i);
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} else {
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printk("%3x", i);
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}
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}
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printk("\r\n");
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for (i = 0; i < 0x10; i++) {
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printk("%1x ", i);
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for (j = 0; j < 0x10; j++) {
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temp = IN3C5B(info->mmio_map, i * 0x10 + j);
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printk("%3x", temp);
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}
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printk("\r\n");
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}
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// 0x3D5
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printk("\r\n====xgi_dump_register=========0x%x===============\r\n",
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0x3D5);
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for (i = 0; i < 0x10; i++) {
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if (i == 0) {
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printk("%5x", i);
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} else {
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printk("%3x", i);
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}
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}
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printk("\r\n");
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for (i = 0; i < 0x10; i++) {
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printk("%1x ", i);
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for (j = 0; j < 0x10; j++) {
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temp = IN3X5B(info->mmio_map, i * 0x10 + j);
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printk("%3x", temp);
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}
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printk("\r\n");
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}
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// 0x3CF
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printk("\r\n=========xgi_dump_register====0x%x===============\r\n",
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0x3CF);
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for (i = 0; i < 0x10; i++) {
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if (i == 0) {
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printk("%5x", i);
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} else {
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printk("%3x", i);
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}
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}
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printk("\r\n");
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for (i = 0; i < 0x10; i++) {
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printk("%1x ", i);
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for (j = 0; j < 0x10; j++) {
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temp = IN3CFB(info->mmio_map, i * 0x10 + j);
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printk("%3x", temp);
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}
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printk("\r\n");
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}
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printk("\r\n=====xgi_dump_register======0x%x===============\r\n",
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0xB000);
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for (i = 0; i < 0x10; i++) {
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if (i == 0) {
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printk("%5x", i);
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} else {
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printk("%3x", i);
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}
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}
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printk("\r\n");
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for (i = 0; i < 0x5; i++) {
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printk("%1x ", i);
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for (j = 0; j < 0x10; j++) {
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temp = DRM_READ8(info->mmio_map, 0xB000 + i * 0x10 + j);
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printk("%3x", temp);
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}
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printk("\r\n");
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}
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printk("\r\n==================0x%x===============\r\n", 0x2200);
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for (i = 0; i < 0x10; i++) {
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if (i == 0) {
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printk("%5x", i);
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} else {
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printk("%3x", i);
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}
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}
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printk("\r\n");
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for (i = 0; i < 0xB; i++) {
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printk("%1x ", i);
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for (j = 0; j < 0x10; j++) {
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temp = DRM_READ8(info->mmio_map, 0x2200 + i * 0x10 + j);
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printk("%3x", temp);
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}
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printk("\r\n");
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}
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printk("\r\n==================0x%x===============\r\n", 0x2300);
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for (i = 0; i < 0x10; i++) {
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if (i == 0) {
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printk("%5x", i);
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} else {
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printk("%3x", i);
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}
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}
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printk("\r\n");
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for (i = 0; i < 0x7; i++) {
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printk("%1x ", i);
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for (j = 0; j < 0x10; j++) {
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temp = DRM_READ8(info->mmio_map, 0x2300 + i * 0x10 + j);
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printk("%3x", temp);
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}
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printk("\r\n");
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}
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printk("\r\n==================0x%x===============\r\n", 0x2400);
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for (i = 0; i < 0x10; i++) {
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if (i == 0) {
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printk("%5x", i);
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} else {
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printk("%3x", i);
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}
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}
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printk("\r\n");
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for (i = 0; i < 0x10; i++) {
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printk("%1x ", i);
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for (j = 0; j < 0x10; j++) {
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temp = DRM_READ8(info->mmio_map, 0x2400 + i * 0x10 + j);
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printk("%3x", temp);
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}
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printk("\r\n");
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}
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printk("\r\n==================0x%x===============\r\n", 0x2800);
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for (i = 0; i < 0x10; i++) {
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if (i == 0) {
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printk("%5x", i);
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} else {
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printk("%3x", i);
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}
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}
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printk("\r\n");
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for (i = 0; i < 0x10; i++) {
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printk("%1x ", i);
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for (j = 0; j < 0x10; j++) {
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temp = DRM_READ8(info->mmio_map, 0x2800 + i * 0x10 + j);
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printk("%3x", temp);
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}
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printk("\r\n");
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}
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}
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int xgi_dump_register_ioctl(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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struct xgi_info *info = dev->dev_private;
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xgi_dump_register(info);
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return 0;
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}
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int xgi_restore_registers_ioctl(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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struct xgi_info *info = dev->dev_private;
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OUT3X5B(info->mmio_map, 0x13, 0);
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OUT3X5B(info->mmio_map, 0x8b, 2);
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return 0;
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}
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void xgi_waitfor_pci_idle(struct xgi_info * info)
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{
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#define WHOLD_GE_STATUS 0x2800
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#define IDLE_MASK ~0x90200000
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int idleCount = 0;
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while (idleCount < 5) {
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if (DRM_READ32(info->mmio_map, WHOLD_GE_STATUS) & IDLE_MASK) {
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idleCount = 0;
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} else {
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idleCount++;
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}
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}
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}
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