686 lines
19 KiB
C
686 lines
19 KiB
C
/*
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* Copyright 2007-8 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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*/
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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#include "atom.h"
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#include <asm/div64.h>
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#include "drm_crtc_helper.h"
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#include "drm_edid.h"
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int radeon_ddc_dump(struct drm_connector *connector);
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static void avivo_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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int i;
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DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
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RADEON_WRITE(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
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RADEON_WRITE(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
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RADEON_WRITE(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
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RADEON_WRITE(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
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RADEON_WRITE(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
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RADEON_WRITE(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
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RADEON_WRITE(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
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RADEON_WRITE(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
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RADEON_WRITE(AVIVO_DC_LUT_RW_MODE, 0);
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RADEON_WRITE(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
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for (i = 0; i < 256; i++) {
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RADEON_WRITE8(AVIVO_DC_LUT_RW_INDEX, i);
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RADEON_WRITE(AVIVO_DC_LUT_30_COLOR,
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(radeon_crtc->lut_r[i] << 22) |
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(radeon_crtc->lut_g[i] << 12) |
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(radeon_crtc->lut_b[i] << 2));
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}
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RADEON_WRITE(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
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}
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static void legacy_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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int i;
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uint32_t dac2_cntl;
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dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2);
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if (radeon_crtc->crtc_id == 0)
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dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
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else
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dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
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RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
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for (i = 0; i < 256; i++) {
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RADEON_WRITE8(RADEON_PALETTE_INDEX, i);
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RADEON_WRITE(RADEON_PALETTE_DATA,
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(radeon_crtc->lut_r[i] << 16) |
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(radeon_crtc->lut_g[i] << 8) |
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(radeon_crtc->lut_b[i] << 0));
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}
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}
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void radeon_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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if (!crtc->enabled)
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return;
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if (radeon_is_avivo(dev_priv))
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avivo_crtc_load_lut(crtc);
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else
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legacy_crtc_load_lut(crtc);
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}
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/** Sets the color ramps on behalf of RandR */
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void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
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u16 blue, int regno)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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if (regno==0)
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DRM_DEBUG("gamma set %d\n", radeon_crtc->crtc_id);
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radeon_crtc->lut_r[regno] = red >> 8;
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radeon_crtc->lut_g[regno] = green >> 8;
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radeon_crtc->lut_b[regno] = blue >> 8;
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}
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static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
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u16 *blue, uint32_t size)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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int i, j;
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if (size != 256)
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return;
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if (crtc->fb->depth == 16) {
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for (i = 0; i < 64; i++) {
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if (i <= 31) {
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for (j = 0; j < 8; j++) {
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radeon_crtc->lut_r[i * 8 + j] = red[i] >> 8;
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radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 8;
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}
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}
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for (j = 0; j < 4; j++)
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radeon_crtc->lut_g[i * 4 + j] = green[i] >> 8;
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}
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} else {
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for (i = 0; i < 256; i++) {
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radeon_crtc->lut_r[i] = red[i] >> 8;
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radeon_crtc->lut_g[i] = green[i] >> 8;
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radeon_crtc->lut_b[i] = blue[i] >> 8;
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}
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}
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radeon_crtc_load_lut(crtc);
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}
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static void radeon_crtc_destroy(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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drm_crtc_cleanup(crtc);
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kfree(radeon_crtc);
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}
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static const struct drm_crtc_funcs radeon_crtc_funcs = {
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.cursor_set = radeon_crtc_cursor_set,
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.cursor_move = radeon_crtc_cursor_move,
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.gamma_set = radeon_crtc_gamma_set,
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.set_config = drm_crtc_helper_set_config,
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.destroy = radeon_crtc_destroy,
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};
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static void radeon_crtc_init(struct drm_device *dev, int index)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_crtc *radeon_crtc;
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int i;
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radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
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// radeon_crtc = kzalloc(sizeof(struct radeon_crtc), GFP_KERNEL);
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if (radeon_crtc == NULL)
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return;
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drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
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drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
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radeon_crtc->crtc_id = index;
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radeon_crtc->mode_set.crtc = &radeon_crtc->base;
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radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
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radeon_crtc->mode_set.num_connectors = 0;
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for (i = 0; i < 256; i++) {
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radeon_crtc->lut_r[i] = i;
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radeon_crtc->lut_g[i] = i;
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radeon_crtc->lut_b[i] = i;
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}
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if (dev_priv->is_atom_bios)
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radeon_atombios_init_crtc(dev, radeon_crtc);
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else
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radeon_legacy_init_crtc(dev, radeon_crtc);
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}
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bool radeon_legacy_setup_enc_conn(struct drm_device *dev)
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{
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radeon_get_legacy_connector_info_from_bios(dev);
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return false;
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}
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bool radeon_setup_enc_conn(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_mode_info *mode_info = &dev_priv->mode_info;
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/* do all the mac and stuff */
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struct drm_connector *connector;
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struct drm_encoder *encoder;
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int i;
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if (dev_priv->is_atom_bios)
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radeon_get_atom_connector_info_from_bios_connector_table(dev);
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else
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radeon_get_legacy_connector_info_from_bios(dev);
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for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
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if (!mode_info->bios_connector[i].valid)
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continue;
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/* add a connector for this */
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if (mode_info->bios_connector[i].connector_type == CONNECTOR_NONE)
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continue;
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connector = radeon_connector_add(dev, i);
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if (!connector)
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continue;
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encoder = NULL;
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/* if we find an LVDS connector */
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if (mode_info->bios_connector[i].connector_type == CONNECTOR_LVDS) {
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encoder = radeon_encoder_lvtma_add(dev, i);
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if (encoder)
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drm_mode_connector_attach_encoder(connector, encoder);
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}
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/* DAC on DVI or VGA */
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if ((mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_I) ||
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(mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_A) ||
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(mode_info->bios_connector[i].connector_type == CONNECTOR_VGA)) {
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encoder = radeon_encoder_atom_dac_add(dev, i, mode_info->bios_connector[i].dac_type, 0);
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if (encoder)
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drm_mode_connector_attach_encoder(connector, encoder);
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}
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/* TMDS on DVI */
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if ((mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_I) ||
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(mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_D)) {
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encoder = radeon_encoder_atom_tmds_add(dev, i, mode_info->bios_connector[i].tmds_type);
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if (encoder)
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drm_mode_connector_attach_encoder(connector, encoder);
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}
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/* TVDAC on DIN */
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if (mode_info->bios_connector[i].connector_type == CONNECTOR_DIN) {
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encoder = radeon_encoder_atom_dac_add(dev, i, mode_info->bios_connector[i].dac_type, 1);
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if (encoder)
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drm_mode_connector_attach_encoder(connector, encoder);
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}
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}
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list_for_each_entry(connector, &dev->mode_config.connector_list, head)
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radeon_ddc_dump(connector);
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return true;
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}
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int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
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{
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struct drm_radeon_private *dev_priv = radeon_connector->base.dev->dev_private;
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struct edid *edid;
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int ret = 0;
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if (!radeon_connector->ddc_bus)
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return -1;
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radeon_i2c_do_lock(radeon_connector, 1);
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edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
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radeon_i2c_do_lock(radeon_connector, 0);
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if (edid) {
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/* update digital bits here */
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if (edid->digital)
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radeon_connector->use_digital = 1;
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else
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radeon_connector->use_digital = 0;
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drm_mode_connector_update_edid_property(&radeon_connector->base, edid);
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ret = drm_add_edid_modes(&radeon_connector->base, edid);
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kfree(edid);
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return ret;
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}
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return -1;
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}
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int radeon_ddc_dump(struct drm_connector *connector)
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{
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struct edid *edid;
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struct radeon_connector *radeon_connector = to_radeon_connector(connector);
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int ret = 0;
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if (!radeon_connector->ddc_bus)
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return -1;
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radeon_i2c_do_lock(radeon_connector, 1);
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edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
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radeon_i2c_do_lock(radeon_connector, 0);
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if (edid) {
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kfree(edid);
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}
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return ret;
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}
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static inline uint32_t radeon_div(uint64_t n, uint32_t d)
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{
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uint64_t x, y, result;
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uint64_t mod;
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n += d / 2;
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mod = do_div(n, d);
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return n;
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}
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void radeon_compute_pll(struct radeon_pll *pll,
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uint64_t freq,
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uint32_t *dot_clock_p,
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uint32_t *fb_div_p,
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uint32_t *ref_div_p,
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uint32_t *post_div_p,
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int flags)
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{
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uint32_t min_ref_div = pll->min_ref_div;
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uint32_t max_ref_div = pll->max_ref_div;
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uint32_t best_vco = pll->best_vco;
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uint32_t best_post_div = 1;
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uint32_t best_ref_div = 1;
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uint32_t best_feedback_div = 1;
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uint32_t best_freq = -1;
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uint32_t best_error = 0xffffffff;
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uint32_t best_vco_diff = 1;
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uint32_t post_div;
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DRM_DEBUG("PLL freq %llu\n", freq);
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freq = freq * 1000;
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if (flags & RADEON_PLL_USE_REF_DIV)
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min_ref_div = max_ref_div = pll->reference_div;
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else {
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while (min_ref_div < max_ref_div-1) {
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uint32_t mid=(min_ref_div+max_ref_div)/2;
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uint32_t pll_in = pll->reference_freq / mid;
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if (pll_in < pll->pll_in_min)
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max_ref_div = mid;
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else if (pll_in > pll->pll_in_max)
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min_ref_div = mid;
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else
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break;
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}
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}
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for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
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uint32_t ref_div;
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if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
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continue;
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/* legacy radeons only have a few post_divs */
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if (flags & RADEON_PLL_LEGACY) {
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if ((post_div == 5) ||
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(post_div == 7) ||
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(post_div == 9) ||
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(post_div == 10) ||
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(post_div == 11) ||
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(post_div == 13) ||
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(post_div == 14) ||
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(post_div == 15))
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continue;
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}
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for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
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uint32_t feedback_div, current_freq, error, vco_diff;
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uint32_t pll_in = pll->reference_freq / ref_div;
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uint32_t min_feed_div = pll->min_feedback_div;
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uint32_t max_feed_div = pll->max_feedback_div+1;
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if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
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continue;
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while (min_feed_div < max_feed_div) {
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uint32_t vco;
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feedback_div = (min_feed_div+max_feed_div)/2;
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vco = radeon_div((uint64_t)pll->reference_freq * feedback_div,
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ref_div);
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if (vco < pll->pll_out_min) {
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min_feed_div = feedback_div+1;
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continue;
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} else if(vco > pll->pll_out_max) {
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max_feed_div = feedback_div;
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continue;
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}
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current_freq = radeon_div((uint64_t)pll->reference_freq * 10000 * feedback_div,
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ref_div * post_div);
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error = abs(current_freq - freq);
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vco_diff = abs(vco - best_vco);
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if ((best_vco == 0 && error < best_error) ||
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(best_vco != 0 &&
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(error < best_error - 100 ||
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(abs(error - best_error) < 100 && vco_diff < best_vco_diff )))) {
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best_post_div = post_div;
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best_ref_div = ref_div;
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best_feedback_div = feedback_div;
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best_freq = current_freq;
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best_error = error;
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best_vco_diff = vco_diff;
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} else if (current_freq == freq) {
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if (best_freq == -1) {
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best_post_div = post_div;
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best_ref_div = ref_div;
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best_feedback_div = feedback_div;
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best_freq = current_freq;
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best_error = error;
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best_vco_diff = vco_diff;
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} else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
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((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
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((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
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((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
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((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
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((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
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best_post_div = post_div;
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best_ref_div = ref_div;
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best_feedback_div = feedback_div;
|
|
best_freq = current_freq;
|
|
best_error = error;
|
|
best_vco_diff = vco_diff;
|
|
}
|
|
}
|
|
|
|
if (current_freq < freq)
|
|
min_feed_div = feedback_div+1;
|
|
else
|
|
max_feed_div = feedback_div;
|
|
}
|
|
}
|
|
}
|
|
|
|
*dot_clock_p = best_freq / 10000;
|
|
*fb_div_p = best_feedback_div;
|
|
*ref_div_p = best_ref_div;
|
|
*post_div_p = best_post_div;
|
|
}
|
|
|
|
void radeon_get_clock_info(struct drm_device *dev)
|
|
{
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
struct radeon_pll *p1pll = &dev_priv->mode_info.p1pll;
|
|
struct radeon_pll *p2pll = &dev_priv->mode_info.p2pll;
|
|
struct radeon_pll *spll = &dev_priv->mode_info.spll;
|
|
struct radeon_pll *mpll = &dev_priv->mode_info.mpll;
|
|
int ret;
|
|
|
|
if (dev_priv->is_atom_bios)
|
|
ret = radeon_atom_get_clock_info(dev);
|
|
else
|
|
ret = radeon_combios_get_clock_info(dev);
|
|
|
|
if (ret) {
|
|
if (p1pll->reference_div < 2)
|
|
p1pll->reference_div = 12;
|
|
if (p2pll->reference_div < 2)
|
|
p2pll->reference_div = 12;
|
|
} else {
|
|
// TODO FALLBACK
|
|
}
|
|
|
|
/* pixel clocks */
|
|
if (radeon_is_avivo(dev_priv)) {
|
|
p1pll->min_post_div = 2;
|
|
p1pll->max_post_div = 0x7f;
|
|
p2pll->min_post_div = 2;
|
|
p2pll->max_post_div = 0x7f;
|
|
} else {
|
|
p1pll->min_post_div = 1;
|
|
p1pll->max_post_div = 16;
|
|
p2pll->min_post_div = 1;
|
|
p2pll->max_post_div = 12;
|
|
}
|
|
|
|
p1pll->min_ref_div = 2;
|
|
p1pll->max_ref_div = 0x3ff;
|
|
p1pll->min_feedback_div = 4;
|
|
p1pll->max_feedback_div = 0x7ff;
|
|
p1pll->best_vco = 0;
|
|
|
|
p2pll->min_ref_div = 2;
|
|
p2pll->max_ref_div = 0x3ff;
|
|
p2pll->min_feedback_div = 4;
|
|
p2pll->max_feedback_div = 0x7ff;
|
|
p2pll->best_vco = 0;
|
|
|
|
/* system clock */
|
|
spll->min_post_div = 1;
|
|
spll->max_post_div = 1;
|
|
spll->min_ref_div = 2;
|
|
spll->max_ref_div = 0xff;
|
|
spll->min_feedback_div = 4;
|
|
spll->max_feedback_div = 0xff;
|
|
spll->best_vco = 0;
|
|
|
|
/* memory clock */
|
|
mpll->min_post_div = 1;
|
|
mpll->max_post_div = 1;
|
|
mpll->min_ref_div = 2;
|
|
mpll->max_ref_div = 0xff;
|
|
mpll->min_feedback_div = 4;
|
|
mpll->max_feedback_div = 0xff;
|
|
mpll->best_vco = 0;
|
|
|
|
}
|
|
|
|
/* not sure of the best place for these */
|
|
/* 10 khz */
|
|
void radeon_legacy_set_engine_clock(struct drm_device *dev, int eng_clock)
|
|
{
|
|
struct drm_radeon_private *dev_priv = dev->dev_private;
|
|
struct radeon_mode_info *mode_info = &dev_priv->mode_info;
|
|
struct radeon_pll *spll = &mode_info->spll;
|
|
uint32_t ref_div, fb_div;
|
|
uint32_t m_spll_ref_fb_div;
|
|
|
|
/* FIXME wait for idle */
|
|
|
|
m_spll_ref_fb_div = RADEON_READ_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV);
|
|
m_spll_ref_fb_div &= ((RADEON_M_SPLL_REF_DIV_MASK << RADEON_M_SPLL_REF_DIV_SHIFT) |
|
|
(RADEON_MPLL_FB_DIV_MASK << RADEON_MPLL_FB_DIV_SHIFT));
|
|
ref_div = m_spll_ref_fb_div & RADEON_M_SPLL_REF_DIV_MASK;
|
|
|
|
fb_div = radeon_div(eng_clock * ref_div, spll->reference_freq);
|
|
m_spll_ref_fb_div |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
|
|
RADEON_WRITE_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV, m_spll_ref_fb_div);
|
|
|
|
}
|
|
|
|
/* 10 khz */
|
|
void radeon_legacy_set_memory_clock(struct drm_device *dev, int mem_clock)
|
|
{
|
|
struct drm_radeon_private *dev_priv = dev->dev_private;
|
|
struct radeon_mode_info *mode_info = &dev_priv->mode_info;
|
|
struct radeon_pll *mpll = &mode_info->mpll;
|
|
uint32_t ref_div, fb_div;
|
|
uint32_t m_spll_ref_fb_div;
|
|
|
|
/* FIXME wait for idle */
|
|
|
|
m_spll_ref_fb_div = RADEON_READ_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV);
|
|
m_spll_ref_fb_div &= ((RADEON_M_SPLL_REF_DIV_MASK << RADEON_M_SPLL_REF_DIV_SHIFT) |
|
|
(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT));
|
|
ref_div = m_spll_ref_fb_div & RADEON_M_SPLL_REF_DIV_MASK;
|
|
|
|
fb_div = radeon_div(mem_clock * ref_div, mpll->reference_freq);
|
|
m_spll_ref_fb_div |= (fb_div & RADEON_MPLL_FB_DIV_MASK) << RADEON_MPLL_FB_DIV_SHIFT;
|
|
RADEON_WRITE_PLL(dev_priv, RADEON_M_SPLL_REF_FB_DIV, m_spll_ref_fb_div);
|
|
|
|
}
|
|
|
|
static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
|
|
{
|
|
struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
|
|
struct drm_device *dev = fb->dev;
|
|
|
|
if (fb->fbdev)
|
|
radeonfb_remove(dev, fb);
|
|
|
|
drm_framebuffer_cleanup(fb);
|
|
kfree(radeon_fb);
|
|
}
|
|
|
|
static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
|
|
struct drm_file *file_priv,
|
|
unsigned int *handle)
|
|
{
|
|
struct drm_gem_object *object = fb->mm_private;
|
|
|
|
return drm_gem_handle_create(file_priv, object, handle);
|
|
}
|
|
|
|
static const struct drm_framebuffer_funcs radeon_fb_funcs = {
|
|
.destroy = radeon_user_framebuffer_destroy,
|
|
.create_handle = radeon_user_framebuffer_create_handle,
|
|
};
|
|
|
|
struct drm_framebuffer *
|
|
radeon_framebuffer_create(struct drm_device *dev,
|
|
struct drm_mode_fb_cmd *mode_cmd,
|
|
void *mm_private)
|
|
{
|
|
struct radeon_framebuffer *radeon_fb;
|
|
|
|
radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
|
|
if (!radeon_fb)
|
|
return NULL;
|
|
|
|
drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
|
|
drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd, mm_private);
|
|
return &radeon_fb->base;
|
|
}
|
|
|
|
static struct drm_framebuffer *
|
|
radeon_user_framebuffer_create(struct drm_device *dev,
|
|
struct drm_file *file_priv,
|
|
struct drm_mode_fb_cmd *mode_cmd)
|
|
{
|
|
struct radeon_framebuffer *radeon_fb;
|
|
void *mm_private;
|
|
|
|
mm_private = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
|
|
return radeon_framebuffer_create(dev, mode_cmd, mm_private);
|
|
}
|
|
|
|
static const struct drm_mode_config_funcs radeon_mode_funcs = {
|
|
.fb_create = radeon_user_framebuffer_create,
|
|
.fb_changed = radeonfb_probe,
|
|
};
|
|
|
|
|
|
int radeon_modeset_init(struct drm_device *dev)
|
|
{
|
|
drm_radeon_private_t *dev_priv = dev->dev_private;
|
|
static struct card_info card;
|
|
size_t size;
|
|
int num_crtc = 2, i;
|
|
int ret;
|
|
|
|
drm_mode_config_init(dev);
|
|
|
|
dev->mode_config.funcs = (void *)&radeon_mode_funcs;
|
|
|
|
if (radeon_is_avivo(dev_priv)) {
|
|
dev->mode_config.max_width = 8192;
|
|
dev->mode_config.max_height = 8192;
|
|
} else {
|
|
dev->mode_config.max_width = 4096;
|
|
dev->mode_config.max_height = 4096;
|
|
}
|
|
|
|
dev->mode_config.fb_base = dev_priv->fb_aper_offset;
|
|
|
|
/* allocate crtcs - TODO single crtc */
|
|
for (i = 0; i < num_crtc; i++) {
|
|
radeon_crtc_init(dev, i);
|
|
}
|
|
|
|
/* okay we should have all the bios connectors */
|
|
|
|
ret = radeon_setup_enc_conn(dev);
|
|
|
|
if (!ret)
|
|
return ret;
|
|
|
|
drm_helper_initial_config(dev, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
int radeon_load_modeset_init(struct drm_device *dev)
|
|
{
|
|
int ret;
|
|
ret = radeon_modeset_init(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void radeon_modeset_cleanup(struct drm_device *dev)
|
|
{
|
|
drm_mode_config_cleanup(dev);
|
|
}
|