310 lines
9.9 KiB
C
310 lines
9.9 KiB
C
/*
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* Copyright © 2008 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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/** @file i915_gem_tiling.c
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*
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* Support for managing tiling state of buffer objects.
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*
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* The idea behind tiling is to increase cache hit rates by rearranging
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* pixel data so that a group of pixel accesses are in the same cacheline.
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* Performance improvement from doing this on the back/depth buffer are on
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* the order of 30%.
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*
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* Intel architectures make this somewhat more complicated, though, by
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* adjustments made to addressing of data when the memory is in interleaved
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* mode (matched pairs of DIMMS) to improve memory bandwidth.
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* For interleaved memory, the CPU sends every sequential 64 bytes
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* to an alternate memory channel so it can get the bandwidth from both.
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*
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* The GPU also rearranges its accesses for increased bandwidth to interleaved
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* memory, and it matches what the CPU does for non-tiled. However, when tiled
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* it does it a little differently, since one walks addresses not just in the
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* X direction but also Y. So, along with alternating channels when bit
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* 6 of the address flips, it also alternates when other bits flip -- Bits 9
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* (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
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* are common to both the 915 and 965-class hardware.
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*
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* The CPU also sometimes XORs in higher bits as well, to improve
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* bandwidth doing strided access like we do so frequently in graphics. This
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* is called "Channel XOR Randomization" in the MCH documentation. The result
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* is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
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* decode.
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*
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* All of this bit 6 XORing has an effect on our memory management,
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* as we need to make sure that the 3d driver can correctly address object
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* contents.
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*
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* If we don't have interleaved memory, all tiling is safe and no swizzling is
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* required.
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*
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* When bit 17 is XORed in, we simply refuse to tile at all. Bit
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* 17 is not just a page offset, so as we page an objet out and back in,
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* individual pages in it will have different bit 17 addresses, resulting in
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* each 64 bytes being swapped with its neighbor!
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*
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* Otherwise, if interleaved, we have to tell the 3d driver what the address
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* swizzling it needs to do is, since it's writing with the CPU to the pages
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* (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
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* pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
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* required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
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* to match what the GPU expects.
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*/
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/**
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* Detects bit 6 swizzling of address lookup between IGD access and CPU
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* access through main memory.
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*/
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void
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i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct pci_dev *bridge;
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uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
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uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
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int mchbar_offset;
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char __iomem *mchbar;
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int ret;
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bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
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if (bridge == NULL) {
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DRM_ERROR("Couldn't get bridge device\n");
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return;
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}
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ret = pci_enable_device(bridge);
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if (ret != 0) {
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DRM_ERROR("pci_enable_device failed: %d\n", ret);
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return;
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}
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if (IS_I965G(dev))
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mchbar_offset = 0x48;
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else
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mchbar_offset = 0x44;
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/* Use resource 2 for our BAR that's stashed in a nonstandard location,
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* since the bridge would only ever use standard BARs 0-1 (though it
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* doesn't anyway)
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*/
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ret = pci_read_base(bridge, mchbar_offset, &bridge->resource[2]);
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if (ret != 0) {
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DRM_ERROR("pci_read_base failed: %d\n", ret);
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return;
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}
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mchbar = ioremap(pci_resource_start(bridge, 2),
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pci_resource_len(bridge, 2));
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if (mchbar == NULL) {
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DRM_ERROR("Couldn't map MCHBAR to determine tile swizzling\n");
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return;
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}
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if (IS_I965G(dev) && !IS_I965GM(dev)) {
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uint32_t chdecmisc;
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/* On the 965, channel interleave appears to be determined by
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* the flex bit. If flex is set, then the ranks (sides of a
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* DIMM) of memory will be "stacked" (physical addresses walk
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* through one rank then move on to the next, flipping channels
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* or not depending on rank configuration). The GPU in this
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* case does exactly the same addressing as the CPU.
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*
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* Unlike the 945, channel randomization based does not
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* appear to be available.
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*
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* XXX: While the G965 doesn't appear to do any interleaving
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* when the DIMMs are not exactly matched, the G4x chipsets
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* might be for "L-shaped" configurations, and will need to be
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* detected.
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*
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* L-shaped configuration:
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*
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* +-----+
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* | |
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* |DIMM2| <-- non-interleaved
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* +-----+
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* +-----+ +-----+
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* | | | |
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* |DIMM0| |DIMM1| <-- interleaved area
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* +-----+ +-----+
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*/
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chdecmisc = readb(mchbar + CHDECMISC);
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if (chdecmisc == 0xff) {
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DRM_ERROR("Couldn't read from MCHBAR. "
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"Disabling tiling.\n");
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} else if (chdecmisc & CHDECMISC_FLEXMEMORY) {
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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} else {
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swizzle_x = I915_BIT_6_SWIZZLE_9_10;
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swizzle_y = I915_BIT_6_SWIZZLE_9;
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}
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} else if (IS_I9XX(dev)) {
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uint32_t dcc;
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/* On 915-945 and GM965, channel interleave by the CPU is
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* determined by DCC. The CPU will alternate based on bit 6
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* in interleaved mode, and the GPU will then also alternate
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* on bit 6, 9, and 10 for X, but the CPU may also optionally
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* alternate based on bit 17 (XOR not disabled and XOR
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* bit == 17).
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*/
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dcc = readl(mchbar + DCC);
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switch (dcc & DCC_ADDRESSING_MODE_MASK) {
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case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
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case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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break;
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case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
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if (IS_I915G(dev) || IS_I915GM(dev) ||
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dcc & DCC_CHANNEL_XOR_DISABLE) {
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swizzle_x = I915_BIT_6_SWIZZLE_9_10;
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swizzle_y = I915_BIT_6_SWIZZLE_9;
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} else if (IS_I965GM(dev)) {
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/* GM965 only does bit 11-based channel
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* randomization
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*/
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swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
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swizzle_y = I915_BIT_6_SWIZZLE_9_11;
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} else {
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/* Bit 17 or perhaps other swizzling */
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swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
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swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
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}
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break;
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}
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if (dcc == 0xffffffff) {
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DRM_ERROR("Couldn't read from MCHBAR. "
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"Disabling tiling.\n");
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swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
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swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
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}
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} else {
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/* As far as we know, the 865 doesn't have these bit 6
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* swizzling issues.
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*/
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swizzle_x = I915_BIT_6_SWIZZLE_NONE;
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swizzle_y = I915_BIT_6_SWIZZLE_NONE;
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}
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iounmap(mchbar);
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dev_priv->mm.bit_6_swizzle_x = swizzle_x;
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dev_priv->mm.bit_6_swizzle_y = swizzle_y;
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}
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/**
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* Sets the tiling mode of an object, returning the required swizzling of
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* bit 6 of addresses in the object.
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*/
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int
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i915_gem_set_tiling(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_i915_gem_set_tiling *args = data;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_gem_object *obj;
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struct drm_i915_gem_object *obj_priv;
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obj = drm_gem_object_lookup(dev, file_priv, args->handle);
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if (obj == NULL)
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return -EINVAL;
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obj_priv = obj->driver_private;
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mutex_lock(&dev->struct_mutex);
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if (args->tiling_mode == I915_TILING_NONE) {
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obj_priv->tiling_mode = I915_TILING_NONE;
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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} else {
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if (args->tiling_mode == I915_TILING_X)
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
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else
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
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/* If we can't handle the swizzling, make it untiled. */
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if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
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args->tiling_mode = I915_TILING_NONE;
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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}
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}
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obj_priv->tiling_mode = args->tiling_mode;
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mutex_unlock(&dev->struct_mutex);
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drm_gem_object_unreference(obj);
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return 0;
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}
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/**
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* Returns the current tiling mode and required bit 6 swizzling for the object.
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*/
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int
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i915_gem_get_tiling(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_i915_gem_get_tiling *args = data;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_gem_object *obj;
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struct drm_i915_gem_object *obj_priv;
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obj = drm_gem_object_lookup(dev, file_priv, args->handle);
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if (obj == NULL)
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return -EINVAL;
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obj_priv = obj->driver_private;
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mutex_lock(&dev->struct_mutex);
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args->tiling_mode = obj_priv->tiling_mode;
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switch (obj_priv->tiling_mode) {
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case I915_TILING_X:
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
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break;
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case I915_TILING_Y:
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args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
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break;
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case I915_TILING_NONE:
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args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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break;
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default:
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DRM_ERROR("unknown tiling mode\n");
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}
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mutex_unlock(&dev->struct_mutex);
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drm_gem_object_unreference(obj);
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return 0;
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}
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