128 lines
3.8 KiB
C
128 lines
3.8 KiB
C
/****************************************************************************
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* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* XGI AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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***************************************************************************/
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#include "xgi_drv.h"
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#include "xgi_regs.h"
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#include "xgi_misc.h"
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void xgi_gart_flush(struct drm_device *dev)
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{
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struct xgi_info *const info = dev->dev_private;
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u8 temp;
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DRM_MEMORYBARRIER();
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/* Set GART in SFB */
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temp = DRM_READ8(info->mmio_map, 0xB00C);
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DRM_WRITE8(info->mmio_map, 0xB00C, temp & ~0x02);
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/* Set GART base address to HW */
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DRM_WRITE32(info->mmio_map, 0xB034, info->gart_info.bus_addr);
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/* Flush GART table. */
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DRM_WRITE8(info->mmio_map, 0xB03F, 0x40);
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DRM_WRITE8(info->mmio_map, 0xB03F, 0x00);
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}
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int xgi_pcie_heap_init(struct xgi_info * info)
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{
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u8 temp = 0;
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int err;
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struct drm_scatter_gather request;
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/* Get current FB aperture size */
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temp = IN3X5B(info->mmio_map, 0x27);
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DRM_INFO("In3x5(0x27): 0x%x \n", temp);
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if (temp & 0x01) { /* 256MB; Jong 06/05/2006; 0x10000000 */
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info->pcie.base = 256 * 1024 * 1024;
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} else { /* 128MB; Jong 06/05/2006; 0x08000000 */
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info->pcie.base = 128 * 1024 * 1024;
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}
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DRM_INFO("info->pcie.base: 0x%lx\n", (unsigned long) info->pcie.base);
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/* Get current lookup table page size */
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temp = DRM_READ8(info->mmio_map, 0xB00C);
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if (temp & 0x04) { /* 8KB */
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info->lutPageSize = 8 * 1024;
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} else { /* 4KB */
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info->lutPageSize = 4 * 1024;
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}
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DRM_INFO("info->lutPageSize: 0x%x \n", info->lutPageSize);
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request.size = info->pcie.size;
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err = drm_sg_alloc(info->dev, & request);
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if (err) {
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DRM_ERROR("cannot allocate PCIE GART backing store! "
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"size = %d\n", info->pcie.size);
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return err;
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}
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info->gart_info.table_mask = DMA_BIT_MASK(32);
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info->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
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info->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
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info->gart_info.table_size = info->dev->sg->pages * sizeof(u32);
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if (!drm_ati_pcigart_init(info->dev, &info->gart_info)) {
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DRM_ERROR("failed to init PCI GART!\n");
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return -ENOMEM;
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}
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xgi_gart_flush(info->dev);
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mutex_lock(&info->dev->struct_mutex);
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err = drm_sman_set_range(&info->sman, XGI_MEMLOC_NON_LOCAL,
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0, info->pcie.size);
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mutex_unlock(&info->dev->struct_mutex);
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if (err) {
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drm_ati_pcigart_cleanup(info->dev, &info->gart_info);
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}
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info->pcie_heap_initialized = (err == 0);
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return err;
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}
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/**
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* xgi_find_pcie_virt
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* @address: GE HW address
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*
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* Returns CPU virtual address. Assumes the CPU VAddr is continuous in not
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* the same block
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*/
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void *xgi_find_pcie_virt(struct xgi_info * info, u32 address)
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{
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const unsigned long offset = address - info->pcie.base;
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return ((u8 *) info->dev->sg->virtual) + offset;
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}
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