152 lines
4.1 KiB
C
152 lines
4.1 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "CUnit/Basic.h"
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#include "amdgpu_test.h"
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#include "amdgpu_drm.h"
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static amdgpu_device_handle device_handle;
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static uint32_t major_version;
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static uint32_t minor_version;
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static void amdgpu_vmid_reserve_test(void);
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int suite_vm_tests_init(void)
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{
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struct amdgpu_gpu_info gpu_info = {0};
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int r;
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r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
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&minor_version, &device_handle);
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if (r) {
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if ((r == -EACCES) && (errno == EACCES))
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printf("\n\nError:%s. "
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"Hint:Try to run this test program as root.",
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strerror(errno));
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return CUE_SINIT_FAILED;
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}
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return CUE_SUCCESS;
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}
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int suite_vm_tests_clean(void)
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{
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int r = amdgpu_device_deinitialize(device_handle);
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if (r == 0)
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return CUE_SUCCESS;
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else
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return CUE_SCLEAN_FAILED;
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}
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CU_TestInfo vm_tests[] = {
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{ "resere vmid test", amdgpu_vmid_reserve_test },
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CU_TEST_INFO_NULL,
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};
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static void amdgpu_vmid_reserve_test(void)
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{
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amdgpu_context_handle context_handle;
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amdgpu_bo_handle ib_result_handle;
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void *ib_result_cpu;
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uint64_t ib_result_mc_address;
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struct amdgpu_cs_request ibs_request;
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struct amdgpu_cs_ib_info ib_info;
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struct amdgpu_cs_fence fence_status;
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uint32_t expired, flags;
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int i, r, instance;
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amdgpu_bo_list_handle bo_list;
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amdgpu_va_handle va_handle;
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union drm_amdgpu_vm vm;
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static uint32_t *ptr;
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r = amdgpu_cs_ctx_create(device_handle, &context_handle);
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CU_ASSERT_EQUAL(r, 0);
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flags = 0;
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r = amdgpu_vm_reserve_vmid(device_handle, flags);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&ib_result_handle, &ib_result_cpu,
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&ib_result_mc_address, &va_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL,
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&bo_list);
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CU_ASSERT_EQUAL(r, 0);
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ptr = ib_result_cpu;
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for (i = 0; i < 16; ++i)
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ptr[i] = 0xffff1000;
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memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info));
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ib_info.ib_mc_address = ib_result_mc_address;
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ib_info.size = 16;
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memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request));
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ibs_request.ip_type = AMDGPU_HW_IP_GFX;
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ibs_request.ring = 0;
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ibs_request.number_of_ibs = 1;
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ibs_request.ibs = &ib_info;
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ibs_request.resources = bo_list;
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ibs_request.fence_info.handle = NULL;
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r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1);
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CU_ASSERT_EQUAL(r, 0);
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memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence));
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fence_status.context = context_handle;
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fence_status.ip_type = AMDGPU_HW_IP_GFX;
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fence_status.ip_instance = 0;
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fence_status.ring = 0;
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fence_status.fence = ibs_request.seq_no;
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r = amdgpu_cs_query_fence_status(&fence_status,
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AMDGPU_TIMEOUT_INFINITE,0, &expired);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_list_destroy(bo_list);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle,
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ib_result_mc_address, 4096);
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CU_ASSERT_EQUAL(r, 0);
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flags = 0;
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r = amdgpu_vm_unreserve_vmid(device_handle, flags);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_ctx_free(context_handle);
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CU_ASSERT_EQUAL(r, 0);
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}
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