416 lines
11 KiB
C
416 lines
11 KiB
C
/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
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/*
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* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
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*
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* The Weather Channel (TM) funded Tungsten Graphics to develop the
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* initial release of the Radeon 8500 driver under the XFree86 license.
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* This notice must be preserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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* Michel D<>zer <michel@daenzer.net>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if (state)
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dev_priv->irq_enable_reg |= mask;
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else
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dev_priv->irq_enable_reg &= ~mask;
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if (dev->irq_enabled)
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RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
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}
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static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if (state)
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dev_priv->r500_disp_irq_reg |= mask;
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else
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dev_priv->r500_disp_irq_reg &= ~mask;
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if (dev->irq_enabled)
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RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
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}
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int radeon_enable_vblank(struct drm_device *dev, int crtc)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
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switch (crtc) {
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case 0:
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r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
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break;
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case 1:
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r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
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break;
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default:
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DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
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crtc);
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return EINVAL;
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}
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} else {
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switch (crtc) {
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case 0:
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radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
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break;
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case 1:
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radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
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break;
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default:
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DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
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crtc);
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return EINVAL;
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}
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}
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return 0;
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}
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void radeon_disable_vblank(struct drm_device *dev, int crtc)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
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switch (crtc) {
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case 0:
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r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
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break;
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case 1:
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r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
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break;
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default:
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DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
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crtc);
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break;
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}
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} else {
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switch (crtc) {
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case 0:
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radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
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break;
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case 1:
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radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
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break;
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default:
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DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
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crtc);
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break;
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}
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}
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}
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static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
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{
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u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
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u32 irq_mask = RADEON_SW_INT_TEST;
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*r500_disp_int = 0;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
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/* vbl interrupts in a different place */
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if (irqs & R500_DISPLAY_INT_STATUS) {
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/* if a display interrupt */
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u32 disp_irq;
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disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
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*r500_disp_int = disp_irq;
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if (disp_irq & R500_D1_VBLANK_INTERRUPT) {
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RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
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}
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if (disp_irq & R500_D2_VBLANK_INTERRUPT) {
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RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
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}
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}
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irq_mask |= R500_DISPLAY_INT_STATUS;
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} else
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irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
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irqs &= irq_mask;
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if (irqs)
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RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
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return irqs;
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}
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/* Interrupts - Used for device synchronization and flushing in the
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* following circumstances:
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*
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* - Exclusive FB access with hw idle:
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* - Wait for GUI Idle (?) interrupt, then do normal flush.
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*
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* - Frame throttling, NV_fence:
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* - Drop marker irq's into command stream ahead of time.
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* - Wait on irq's with lock *not held*
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* - Check each for termination condition
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*
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* - Internally in cp_getbuffer, etc:
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* - as above, but wait with lock held???
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*
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* NOTE: These functions are misleadingly named -- the irq's aren't
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* tied to dma at all, this is just a hangover from dri prehistory.
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*/
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irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *) dev->dev_private;
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u32 stat;
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u32 r500_disp_int;
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u32 tmp;
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/* Only consider the bits we're interested in - others could be used
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* outside the DRM
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*/
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stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
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if (!stat)
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return IRQ_NONE;
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stat &= dev_priv->irq_enable_reg;
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/* SW interrupt */
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if (stat & RADEON_SW_INT_TEST)
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DRM_WAKEUP(&dev_priv->swi_queue);
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/* VBLANK interrupt */
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
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if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
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drm_handle_vblank(dev, 0);
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if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
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drm_handle_vblank(dev, 1);
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} else {
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if (stat & RADEON_CRTC_VBLANK_STAT)
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drm_handle_vblank(dev, 0);
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if (stat & RADEON_CRTC2_VBLANK_STAT)
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drm_handle_vblank(dev, 1);
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}
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if (dev->msi_enabled) {
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switch(dev_priv->flags & RADEON_FAMILY_MASK) {
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case CHIP_RS400:
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case CHIP_RS480:
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tmp = RADEON_READ(RADEON_AIC_CNTL) &
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~RS400_MSI_REARM;
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RADEON_WRITE(RADEON_AIC_CNTL, tmp);
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RADEON_WRITE(RADEON_AIC_CNTL,
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tmp | RS400_MSI_REARM);
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break;
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case CHIP_RS690:
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case CHIP_RS740:
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tmp = RADEON_READ(RADEON_BUS_CNTL) &
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~RS600_MSI_REARM;
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RADEON_WRITE(RADEON_BUS_CNTL, tmp);
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RADEON_WRITE(RADEON_BUS_CNTL, tmp |
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RS600_MSI_REARM);
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break;
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default:
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tmp = RADEON_READ(RADEON_MSI_REARM_EN) &
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~RV370_MSI_REARM_EN;
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RADEON_WRITE(RADEON_MSI_REARM_EN, tmp);
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RADEON_WRITE(RADEON_MSI_REARM_EN,
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tmp | RV370_MSI_REARM_EN);
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break;
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}
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}
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return IRQ_HANDLED;
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}
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static int radeon_emit_irq(struct drm_device * dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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unsigned int ret;
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RING_LOCALS;
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atomic_inc(&dev_priv->swi_emitted);
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ret = atomic_read(&dev_priv->swi_emitted);
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BEGIN_RING(4);
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OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
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OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
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ADVANCE_RING();
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COMMIT_RING();
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return ret;
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}
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static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
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{
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *) dev->dev_private;
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int ret = 0;
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if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
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return 0;
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dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
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DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
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RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
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return ret;
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}
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u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if (!dev_priv) {
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DRM_ERROR("called with no initialization\n");
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return -EINVAL;
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}
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if (crtc < 0 || crtc > 1) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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return -EINVAL;
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}
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
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if (crtc == 0)
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return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
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else
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return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
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} else {
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if (crtc == 0)
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return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
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else
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return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
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}
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}
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/* Needs the lock as it touches the ring.
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*/
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int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_irq_emit_t *emit = data;
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int result;
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LOCK_TEST_WITH_RETURN(dev, file_priv);
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if (!dev_priv) {
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DRM_ERROR("called with no initialization\n");
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return -EINVAL;
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}
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result = radeon_emit_irq(dev);
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if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
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DRM_ERROR("copy_to_user\n");
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return -EFAULT;
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}
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return 0;
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}
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/* Doesn't need the hardware lock.
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*/
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int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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drm_radeon_irq_wait_t *irqwait = data;
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if (!dev_priv) {
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DRM_ERROR("called with no initialization\n");
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return -EINVAL;
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}
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return radeon_wait_irq(dev, irqwait->irq_seq);
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}
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/* drm_dma.h hooks
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*/
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void radeon_driver_irq_preinstall(struct drm_device * dev)
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{
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *) dev->dev_private;
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u32 dummy;
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/* Disable *all* interrupts */
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
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RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
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RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
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/* Clear bits if they're already high */
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radeon_acknowledge_irqs(dev_priv, &dummy);
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}
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int radeon_driver_irq_postinstall(struct drm_device * dev)
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{
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *) dev->dev_private;
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atomic_set(&dev_priv->swi_emitted, 0);
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DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
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dev->max_vblank_count = 0x001fffff;
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radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
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return 0;
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}
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void radeon_driver_irq_uninstall(struct drm_device * dev)
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{
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *) dev->dev_private;
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if (!dev_priv)
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return;
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dev_priv->irq_enabled = 0;
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if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
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RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
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/* Disable *all* interrupts */
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RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
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}
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int radeon_vblank_crtc_get(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
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return dev_priv->vblank_crtc;
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}
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int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
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{
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drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
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if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
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DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
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return -EINVAL;
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}
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dev_priv->vblank_crtc = (unsigned int)value;
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return 0;
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}
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