394 lines
13 KiB
C
394 lines
13 KiB
C
/*
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* Copyright 2005-2006 Stephane Marchesin
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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/* returns the number of hw fifos */
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int nouveau_fifo_number(drm_device_t* dev)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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switch(dev_priv->card_type)
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{
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case NV_03:
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return 8;
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case NV_04:
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case NV_05:
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return 16;
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default:
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return 32;
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}
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}
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/***********************************
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* functions doing the actual work
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***********************************/
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/* voir nv_xaa.c : NVResetGraphics
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* mémoire mappée par nv_driver.c : NVMapMem
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* voir nv_driver.c : NVPreInit
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*/
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static void nouveau_fifo_init(drm_device_t* dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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/* Init PFIFO - This is an exact copy of what's done in the Xorg ddx so far.
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* We should be able to figure out what's happening from the
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* resources available..
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*/
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if (dev->irq_enabled)
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nouveau_irq_postinstall(dev);
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if (dev_priv->card_type >= NV_40)
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NV_WRITE(NV_PGRAPH_NV40_UNK220, dev_priv->fb_obj->instance >> 4);
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DRM_DEBUG("%s: setting FIFO %d active\n", __func__, dev_priv->cur_fifo);
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NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
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NV_WRITE(NV_PFIFO_MODE, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
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if (dev_priv->card_type >= NV_40)
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NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|dev_priv->cur_fifo);
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else
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NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|dev_priv->cur_fifo);
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NV_WRITE(NV_PFIFO_CACH1_DMAP, dev_priv->cur_fifo * dev_priv->cmdbuf_ch_size);
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NV_WRITE(NV_PFIFO_CACH1_DMAG, dev_priv->cur_fifo * dev_priv->cmdbuf_ch_size);
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NV_WRITE(NV_PFIFO_CACH1_DMAI, dev_priv->cmdbuf_obj->instance >> 4);
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NV_WRITE(NV_PFIFO_CACH0_PSH0, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000);
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NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF);
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NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
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NV_WRITE(NV_PFIFO_RAMHT,
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(0x03 << 24) /* search 128 */ |
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((dev_priv->objs.ht_bits - 9) << 16) |
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(dev_priv->objs.ht_base >> 8)
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);
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dev_priv->ramfc_offset=0x11000;
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dev_priv->ramro_offset=0x11200;
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NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8); /* RAMIN+0x11000 0.5k */
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NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8); /* RAMIN+0x11200 0.5k */
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NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
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NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
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NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
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#ifdef __BIG_ENDIAN
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NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
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#else
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NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
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#endif
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NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
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NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
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NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
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NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
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NV_WRITE(NV_PGRAPH_CTX_USER, 0x0);
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NV_WRITE(NV_PFIFO_DELAY_0, 0xff /* retrycount*/ );
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if (dev_priv->card_type >= NV_40)
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NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x00002001);
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else
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NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10110000);
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NV_WRITE(NV_PFIFO_DMA_TIMESLICE, 0x001fffff);
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NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
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DRM_DEBUG("%s: CACHE1 GET/PUT readback %d/%d\n", __func__,
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NV_READ(NV_PFIFO_CACH1_DMAG),
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NV_READ(NV_PFIFO_CACH1_DMAP));
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DRM_INFO("%s: OK\n", __func__);
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}
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static int nouveau_dma_init(struct drm_device *dev)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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struct nouveau_config *config = &dev_priv->config;
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struct mem_block *cb;
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int cb_min_size = nouveau_fifo_number(dev) * NV03_FIFO_SIZE;
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/* XXX this should be done earlier on init */
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nouveau_hash_table_init(dev);
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if (dev_priv->card_type >= NV_40)
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dev_priv->fb_obj = nouveau_dma_object_create(dev,
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0, nouveau_mem_fb_amount(dev),
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NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM);
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/* Defaults for unconfigured values */
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if (!config->cmdbuf.location)
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config->cmdbuf.location = NOUVEAU_MEM_FB;
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if (!config->cmdbuf.size || config->cmdbuf.size < cb_min_size)
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config->cmdbuf.size = cb_min_size;
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cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size,
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config->cmdbuf.location, (DRMFILE)-2);
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/* Try defaults if that didn't succeed */
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if (!cb) {
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config->cmdbuf.location = NOUVEAU_MEM_FB;
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config->cmdbuf.size = cb_min_size;
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cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size,
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config->cmdbuf.location, (DRMFILE)-2);
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}
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if (!cb) {
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DRM_ERROR("Couldn't allocate DMA command buffer.\n");
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return DRM_ERR(ENOMEM);
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}
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if (config->cmdbuf.location == NOUVEAU_MEM_AGP)
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dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev,
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cb->start, cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP);
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else
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dev_priv->cmdbuf_obj = nouveau_dma_object_create(dev,
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cb->start - drm_get_resource_start(dev, 1),
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cb->size, NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM);
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dev_priv->cmdbuf_ch_size = (uint32_t)cb->size / nouveau_fifo_number(dev);
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dev_priv->cmdbuf_alloc = cb;
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nouveau_fifo_init(dev);
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DRM_INFO("DMA command buffer is %dKiB at 0x%08x(%s)\n",
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(uint32_t)cb->size>>10, (uint32_t)cb->start,
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config->cmdbuf.location == NOUVEAU_MEM_FB ? "VRAM" : "AGP");
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DRM_INFO("FIFO size is %dKiB\n", dev_priv->cmdbuf_ch_size>>10);
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return 0;
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}
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/* allocates and initializes a fifo for user space consumption */
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static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, DRMFILE filp)
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{
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int i;
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int ret;
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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uint32_t ctx_addr,ctx_size;
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/* Init cmdbuf on first FIFO init, this is delayed until now to
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* give the ddx a chance to configure the cmdbuf with SETPARAM
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*/
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if (!dev_priv->cmdbuf_alloc) {
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ret = nouveau_dma_init(dev);
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if (ret)
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return ret;
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}
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/*
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* Alright, here is the full story
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* Nvidia cards have multiple hw fifo contexts (praise them for that,
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* no complicated crash-prone context switches)
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* We allocate a new context for each app and let it write to it directly
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* (woo, full userspace command submission !)
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* When there are no more contexts, you lost
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*/
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for(i=0;i<nouveau_fifo_number(dev);i++)
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if (dev_priv->fifos[i].used==0)
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break;
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DRM_INFO("Allocating FIFO number %d\n", i);
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/* no more fifos. you lost. */
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if (i==nouveau_fifo_number(dev))
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return DRM_ERR(EINVAL);
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/* that fifo is used */
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dev_priv->fifos[i].used=1;
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dev_priv->fifos[i].filp=filp;
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init->channel = i;
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init->put_base = i*dev_priv->cmdbuf_ch_size;
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dev_priv->cur_fifo = init->channel;
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nouveau_wait_for_idle(dev);
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/* disable the fifo caches */
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NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
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if (dev_priv->card_type <= NV_05)
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ctx_size=32;
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else
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ctx_size=128;
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ctx_addr=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size;
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// clear the fifo context
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for(i=0;i<ctx_size/4;i++)
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NV_WRITE(ctx_addr+4*i,0x0);
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NV_WRITE(ctx_addr,init->put_base);
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NV_WRITE(ctx_addr+4,init->put_base);
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if (dev_priv->card_type <= NV_05)
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{
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// that's what is done in nvosdk, but that part of the code is buggy so...
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NV_WRITE(ctx_addr+8,dev_priv->cmdbuf_obj->instance >> 4);
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#ifdef __BIG_ENDIAN
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NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
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#else
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NV_WRITE(ctx_addr+16,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
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#endif
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}
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else
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{
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NV_WRITE(ctx_addr+12,dev_priv->cmdbuf_obj->instance >> 4/*DMA INST/DMA COUNT*/);
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#ifdef __BIG_ENDIAN
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NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
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#else
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NV_WRITE(ctx_addr+20,NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
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#endif
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}
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/* enable the fifo dma operation */
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NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel));
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// FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF);
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if (dev_priv->card_type >= NV_40)
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NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|dev_priv->cur_fifo);
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else
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NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|dev_priv->cur_fifo);
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NV_WRITE(NV_PFIFO_CACH1_DMAP, init->put_base);
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NV_WRITE(NV_PFIFO_CACH1_DMAG, init->put_base);
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NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base);
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NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base);
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/* reenable the fifo caches */
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NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
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/* make the fifo available to user space */
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/* first, the fifo control regs */
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init->ctrl = dev_priv->mmio->offset + NV03_FIFO_REGS(init->channel);
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init->ctrl_size = NV03_FIFO_REGS_SIZE;
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ret = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS,
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0, &dev_priv->fifos[init->channel].regs);
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if (ret != 0)
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return ret;
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/* then, the fifo itself */
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init->cmdbuf = dev_priv->cmdbuf_alloc->start;
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init->cmdbuf += init->channel * dev_priv->cmdbuf_ch_size;
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init->cmdbuf_size = dev_priv->cmdbuf_ch_size;
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ret = drm_addmap(dev, init->cmdbuf, init->cmdbuf_size, _DRM_REGISTERS,
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0, &dev_priv->fifos[init->channel].map);
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if (ret != 0)
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return ret;
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/* FIFO has no objects yet */
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dev_priv->fifos[init->channel].objs = NULL;
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DRM_INFO("%s: initialised FIFO %d\n", __func__, init->channel);
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return 0;
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}
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/* stops a fifo */
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void nouveau_fifo_free(drm_device_t* dev,int n)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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dev_priv->fifos[n].used=0;
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DRM_INFO("%s: freeing fifo %d\n", __func__, n);
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/* disable the fifo caches */
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NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
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NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)&~(1<<n));
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// FIXME XXX needs more code
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/* reenable the fifo caches */
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NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
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}
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/* cleanups all the fifos from filp */
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void nouveau_fifo_cleanup(drm_device_t* dev, DRMFILE filp)
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{
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int i;
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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DRM_DEBUG("clearing FIFO enables from filp\n");
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for(i=0;i<nouveau_fifo_number(dev);i++)
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if (dev_priv->fifos[i].filp==filp)
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nouveau_fifo_free(dev,i);
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/* check we still point at an active channel */
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if (dev_priv->fifos[dev_priv->cur_fifo].used == 0) {
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DRM_DEBUG("%s: cur_fifo is no longer owned.\n", __func__);
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for (i=0;i<nouveau_fifo_number(dev);i++)
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if (dev_priv->fifos[i].used) break;
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if (i==nouveau_fifo_number(dev))
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i=0;
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DRM_DEBUG("%s: new cur_fifo is %d\n", __func__, i);
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dev_priv->cur_fifo = i;
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}
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/* if (dev_priv->cmdbuf_alloc)
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nouveau_fifo_init(dev);*/
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}
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int nouveau_fifo_id_get(drm_device_t* dev, DRMFILE filp)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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int i;
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for(i=0;i<nouveau_fifo_number(dev);i++)
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if (dev_priv->fifos[i].filp == filp)
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return i;
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return -1;
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}
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/***********************************
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* ioctls wrapping the functions
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***********************************/
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static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS)
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{
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DRM_DEVICE;
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drm_nouveau_fifo_alloc_t init;
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int res;
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DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data, sizeof(init));
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res=nouveau_fifo_alloc(dev,&init,filp);
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if (!res)
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DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data, init, sizeof(init));
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return res;
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}
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/***********************************
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* finally, the ioctl table
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***********************************/
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drm_ioctl_desc_t nouveau_ioctls[] = {
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[DRM_IOCTL_NR(DRM_NOUVEAU_FIFO_ALLOC)] = {nouveau_ioctl_fifo_alloc, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_NOUVEAU_OBJECT_INIT)] = {nouveau_ioctl_object_init, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_NOUVEAU_DMA_OBJECT_INIT)] = {nouveau_ioctl_dma_object_init, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_NOUVEAU_MEM_ALLOC)] = {nouveau_ioctl_mem_alloc, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_NOUVEAU_MEM_FREE)] = {nouveau_ioctl_mem_free, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_NOUVEAU_GETPARAM)] = {nouveau_ioctl_getparam, DRM_AUTH},
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[DRM_IOCTL_NR(DRM_NOUVEAU_SETPARAM)] = {nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
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};
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int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
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