468 lines
30 KiB
C
468 lines
30 KiB
C
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#define NV03_BOOT_0 0x00100000
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# define NV03_BOOT_0_RAM_AMOUNT 0x00000003
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# define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000
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# define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001
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# define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002
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# define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003
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# define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000
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# define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001
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# define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002
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# define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003
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#define NV04_FIFO_DATA 0x0010020c
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# define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
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# define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
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#define NV03_PGRAPH_STATUS 0x004006b0
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#define NV04_PGRAPH_STATUS 0x00400700
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#define NV_RAMIN 0x00700000
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#define NV_RAMHT_HANDLE_OFFSET 0
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#define NV_RAMHT_CONTEXT_OFFSET 4
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# define NV_RAMHT_CONTEXT_VALID (1<<31)
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# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24
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# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16
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# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0
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# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1
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# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0
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# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23
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# define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20
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# define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0
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/* DMA object defines */
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#define NV_DMA_ACCESS_RW 0
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#define NV_DMA_ACCESS_RO 1
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#define NV_DMA_ACCESS_WO 2
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#define NV_DMA_TARGET_VIDMEM 0
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#define NV_DMA_TARGET_PCI 2
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#define NV_DMA_TARGET_AGP 3
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/* Some object classes we care about in the drm */
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#define NV_CLASS_DMA_FROM_MEMORY 0x00000002
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#define NV_CLASS_DMA_TO_MEMORY 0x00000003
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#define NV_CLASS_NULL 0x00000030
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#define NV_CLASS_DMA_IN_MEMORY 0x0000003D
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#define NV03_FIFO_SIZE 0x8000UL
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#define NV_MAX_FIFO_NUMBER 32
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#define NV03_FIFO_REGS_SIZE 0x10000
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#define NV03_FIFO_REGS(i) (0x00800000+i*NV03_FIFO_REGS_SIZE)
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# define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40)
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# define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44)
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#define NV03_PMC_BOOT_0 0x00000000
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#define NV03_PMC_INTR_0 0x00000100
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# define NV_PMC_INTR_0_PFIFO_PENDING (1<< 8)
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# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12)
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# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24)
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# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25)
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# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24)
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#define NV03_PMC_INTR_EN_0 0x00000140
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# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<< 0)
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#define NV03_PMC_ENABLE 0x00000200
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# define NV_PMC_ENABLE_PFIFO (1<< 8)
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# define NV_PMC_ENABLE_PGRAPH (1<<12)
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/* Disabling the below bit breaks newer (G7X only?) mobile chipsets,
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* the card will hang early on in the X init process.
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*/
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# define NV_PMC_ENABLE_UNK13 (1<<13)
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#define NV40_PMC_1700 0x00001700
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#define NV40_PMC_1704 0x00001704
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#define NV40_PMC_1708 0x00001708
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#define NV40_PMC_170C 0x0000170C
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#define NV04_PTIMER_INTR_0 0x00009100
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#define NV04_PTIMER_INTR_EN_0 0x00009140
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#define NV04_PTIMER_NUMERATOR 0x00009200
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#define NV04_PTIMER_DENOMINATOR 0x00009210
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#define NV04_PTIMER_TIME_0 0x00009400
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#define NV04_PTIMER_TIME_1 0x00009410
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#define NV04_PTIMER_ALARM_0 0x00009420
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#define NV04_PFB_CFG0 0x00100200
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#define NV04_PFB_CFG1 0x00100204
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#define NV40_PFB_020C 0x0010020C
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#define NV10_PFB_TILE(i) (0x00100240 + (i*16))
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#define NV10_PFB_TILE__SIZE 8
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#define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16))
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#define NV10_PFB_TSIZE(i) (0x00100248 + (i*16))
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#define NV10_PFB_TSTATUS(i) (0x0010024C + (i*16))
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#define NV10_PFB_CLOSE_PAGE2 0x0010033C
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#define NV40_PFB_TILE(i) (0x00100600 + (i*16))
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#define NV40_PFB_TILE__SIZE_0 12
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#define NV40_PFB_TILE__SIZE_1 15
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#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))
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#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))
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#define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16))
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#define NV04_PGRAPH_DEBUG_0 0x00400080
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#define NV04_PGRAPH_DEBUG_1 0x00400084
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#define NV04_PGRAPH_DEBUG_2 0x00400088
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#define NV04_PGRAPH_DEBUG_3 0x0040008c
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#define NV10_PGRAPH_DEBUG_4 0x00400090
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#define NV03_PGRAPH_INTR 0x00400100
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#define NV03_PGRAPH_INTR_EN 0x00400140
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#define NV40_PGRAPH_INTR_EN 0x0040013C
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# define NV_PGRAPH_INTR_NOTIFY (1<< 0)
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# define NV_PGRAPH_INTR_MISSING_HW (1<< 4)
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# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12)
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# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16)
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# define NV_PGRAPH_INTR_ERROR (1<<20)
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#define NV10_PGRAPH_CTX_CONTROL 0x00400144
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#define NV10_PGRAPH_CTX_USER 0x00400148
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#define NV10_PGRAPH_CTX_SWITCH1 0x0040014C
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#define NV10_PGRAPH_CTX_SWITCH2 0x00400150
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#define NV10_PGRAPH_CTX_SWITCH3 0x00400154
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#define NV10_PGRAPH_CTX_SWITCH4 0x00400158
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#define NV10_PGRAPH_CTX_SWITCH5 0x0040015C
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#define NV04_PGRAPH_CTX_SWITCH1 0x00400160
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#define NV10_PGRAPH_CTX_CACHE1 0x00400160
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#define NV04_PGRAPH_CTX_SWITCH2 0x00400164
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#define NV04_PGRAPH_CTX_SWITCH3 0x00400168
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#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C
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#define NV04_PGRAPH_CTX_CONTROL 0x00400170
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#define NV04_PGRAPH_CTX_USER 0x00400174
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#define NV04_PGRAPH_CTX_CACHE1 0x00400180
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#define NV10_PGRAPH_CTX_CACHE2 0x00400180
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#define NV03_PGRAPH_CTX_CONTROL 0x00400190
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#define NV03_PGRAPH_CTX_USER 0x00400194
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#define NV04_PGRAPH_CTX_CACHE2 0x004001A0
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#define NV10_PGRAPH_CTX_CACHE3 0x004001A0
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#define NV04_PGRAPH_CTX_CACHE3 0x004001C0
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#define NV10_PGRAPH_CTX_CACHE4 0x004001C0
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#define NV04_PGRAPH_CTX_CACHE4 0x004001E0
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#define NV10_PGRAPH_CTX_CACHE5 0x004001E0
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#define NV03_PGRAPH_ABS_X_RAM 0x00400400
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#define NV03_PGRAPH_ABS_Y_RAM 0x00400480
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#define NV03_PGRAPH_X_MISC 0x00400500
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#define NV03_PGRAPH_Y_MISC 0x00400504
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#define NV04_PGRAPH_VALID1 0x00400508
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#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C
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#define NV04_PGRAPH_MISC24_0 0x00400510
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#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514
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#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518
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#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C
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#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520
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#define NV03_PGRAPH_CLIPX_0 0x00400524
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#define NV03_PGRAPH_CLIPX_1 0x00400528
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#define NV03_PGRAPH_CLIPY_0 0x0040052C
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#define NV03_PGRAPH_CLIPY_1 0x00400530
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#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534
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#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538
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#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
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#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540
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#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544
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#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548
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#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560
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#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564
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#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568
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#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C
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#define NV04_PGRAPH_MISC24_1 0x00400570
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#define NV04_PGRAPH_MISC24_2 0x00400574
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#define NV04_PGRAPH_VALID2 0x00400578
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#define NV04_PGRAPH_PASSTHRU_0 0x0040057C
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#define NV04_PGRAPH_PASSTHRU_1 0x00400580
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#define NV04_PGRAPH_PASSTHRU_2 0x00400584
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#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588
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#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C
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#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590
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#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594
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#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598
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#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C
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#define NV04_PGRAPH_FORMAT_0 0x004005A8
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#define NV04_PGRAPH_FORMAT_1 0x004005AC
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#define NV04_PGRAPH_FILTER_0 0x004005B0
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#define NV04_PGRAPH_FILTER_1 0x004005B4
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#define NV03_PGRAPH_MONO_COLOR0 0x00400600
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#define NV04_PGRAPH_ROP3 0x00400604
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#define NV04_PGRAPH_BETA_AND 0x00400608
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#define NV04_PGRAPH_BETA_PREMULT 0x0040060C
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#define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610
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#define NV04_PGRAPH_FORMATS 0x00400618
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#define NV10_PGRAPH_DEBUG_2 0x00400620
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#define NV04_PGRAPH_BOFFSET0 0x00400640
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#define NV04_PGRAPH_BOFFSET1 0x00400644
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#define NV04_PGRAPH_BOFFSET2 0x00400648
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#define NV04_PGRAPH_BOFFSET3 0x0040064C
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#define NV04_PGRAPH_BOFFSET4 0x00400650
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#define NV04_PGRAPH_BOFFSET5 0x00400654
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#define NV04_PGRAPH_BBASE0 0x00400658
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#define NV04_PGRAPH_BBASE1 0x0040065C
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#define NV04_PGRAPH_BBASE2 0x00400660
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#define NV04_PGRAPH_BBASE3 0x00400664
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#define NV04_PGRAPH_BBASE4 0x00400668
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#define NV04_PGRAPH_BBASE5 0x0040066C
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#define NV04_PGRAPH_BPITCH0 0x00400670
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#define NV04_PGRAPH_BPITCH1 0x00400674
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#define NV04_PGRAPH_BPITCH2 0x00400678
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#define NV04_PGRAPH_BPITCH3 0x0040067C
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#define NV04_PGRAPH_BPITCH4 0x00400680
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#define NV04_PGRAPH_BLIMIT0 0x00400684
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#define NV04_PGRAPH_BLIMIT1 0x00400688
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#define NV04_PGRAPH_BLIMIT2 0x0040068C
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#define NV04_PGRAPH_BLIMIT3 0x00400690
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#define NV04_PGRAPH_BLIMIT4 0x00400694
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#define NV04_PGRAPH_BLIMIT5 0x00400698
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#define NV04_PGRAPH_BSWIZZLE2 0x0040069C
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#define NV04_PGRAPH_BSWIZZLE5 0x004006A0
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#define NV04_PGRAPH_SURFACE 0x0040070C
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#define NV04_PGRAPH_STATE 0x00400710
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#define NV10_PGRAPH_SURFACE 0x00400710
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#define NV04_PGRAPH_NOTIFY 0x00400714
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#define NV10_PGRAPH_STATE 0x00400714
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#define NV10_PGRAPH_NOTIFY 0x00400718
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#define NV04_PGRAPH_FIFO 0x00400720
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#define NV04_PGRAPH_BPIXEL 0x00400724
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#define NV10_PGRAPH_RDI_INDEX 0x00400750
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#define NV04_PGRAPH_FFINTFC_ST2 0x00400754
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#define NV10_PGRAPH_RDI_DATA 0x00400754
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#define NV04_PGRAPH_DMA_PITCH 0x00400760
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#define NV10_PGRAPH_FFINTFC_ST2 0x00400764
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#define NV04_PGRAPH_DVD_COLORFMT 0x00400764
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#define NV04_PGRAPH_SCALED_FORMAT 0x00400768
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#define NV10_PGRAPH_DMA_PITCH 0x00400770
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#define NV10_PGRAPH_DVD_COLORFMT 0x00400774
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#define NV10_PGRAPH_SCALED_FORMAT 0x00400778
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#define NV10_PGRAPH_CHANNEL_CTX_TABLE 0x00400780
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#define NV10_PGRAPH_CHANNEL_CTX_SIZE 0x00400784
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#define NV10_PGRAPH_CHANNEL_CTX_POINTER 0x00400788
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#define NV04_PGRAPH_PATT_COLOR0 0x00400800
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#define NV04_PGRAPH_PATT_COLOR1 0x00400804
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#define NV04_PGRAPH_PATTERN 0x00400808
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#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810
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#define NV04_PGRAPH_CHROMA 0x00400814
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#define NV04_PGRAPH_CONTROL0 0x00400818
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#define NV04_PGRAPH_CONTROL1 0x0040081C
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#define NV04_PGRAPH_CONTROL2 0x00400820
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#define NV04_PGRAPH_BLEND 0x00400824
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#define NV04_PGRAPH_STORED_FMT 0x00400830
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#define NV04_PGRAPH_PATT_COLORRAM 0x00400900
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#define NV40_PGRAPH_TILE0(i) 0x00400900
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#define NV40_PGRAPH_TLIMIT0(i) 0x00400904
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#define NV40_PGRAPH_TSIZE0(i) 0x00400908
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#define NV40_PGRAPH_TSTATUS0(i) 0x0040090C
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#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16))
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#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16))
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#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16))
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#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16))
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#define NV04_PGRAPH_U_RAM 0x00400D00
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#define NV47_PGRAPH_TILE0(i) 0x00400D00
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#define NV47_PGRAPH_TLIMIT0(i) 0x00400D04
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#define NV47_PGRAPH_TSIZE0(i) 0x00400D08
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#define NV47_PGRAPH_TSTATUS0(i) 0x00400D0C
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#define NV04_PGRAPH_V_RAM 0x00400D40
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#define NV04_PGRAPH_W_RAM 0x00400D80
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#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00
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#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20
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#define NV10_PGRAPH_XFMODE0 0x00400F40
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#define NV10_PGRAPH_XFMODE1 0x00400F44
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#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48
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#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C
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#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50
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#define NV10_PGRAPH_PIPE_DATA 0x00400F54
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#define NV04_PGRAPH_DMA_START_0 0x00401000
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#define NV04_PGRAPH_DMA_START_1 0x00401004
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#define NV04_PGRAPH_DMA_LENGTH 0x00401008
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#define NV04_PGRAPH_DMA_MISC 0x0040100C
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#define NV04_PGRAPH_DMA_DATA_0 0x00401020
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#define NV04_PGRAPH_DMA_DATA_1 0x00401024
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#define NV04_PGRAPH_DMA_RM 0x00401030
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#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040
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#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044
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#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048
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#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C
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#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050
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#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054
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#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058
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#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C
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#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060
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#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080
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#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084
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#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088
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#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C
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#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090
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#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094
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#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098
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#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C
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#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0
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#define NV40_PGRAPH_TILE1(i) 0x00406900
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#define NV40_PGRAPH_TLIMIT1(i) 0x00406904
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#define NV40_PGRAPH_TSIZE1(i) 0x00406908
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#define NV40_PGRAPH_TSTATUS1(i) 0x0040690C
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/* It's a guess that this works on NV03. Confirmed on NV04, though */
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#define NV04_PFIFO_DELAY_0 0x00002040
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#define NV04_PFIFO_DMA_TIMESLICE 0x00002044
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#define NV04_PFIFO_NEXT_CHANNEL 0x00002050
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#define NV03_PFIFO_INTR_0 0x00002100
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#define NV03_PFIFO_INTR_EN_0 0x00002140
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# define NV_PFIFO_INTR_CACHE_ERROR (1<< 0)
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# define NV_PFIFO_INTR_RUNOUT (1<< 4)
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# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8)
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# define NV_PFIFO_INTR_DMA_PUSHER (1<<12)
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# define NV_PFIFO_INTR_DMA_PT (1<<16)
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# define NV_PFIFO_INTR_SEMAPHORE (1<<20)
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# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)
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#define NV03_PFIFO_RAMHT 0x00002210
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#define NV03_PFIFO_RAMFC 0x00002214
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#define NV03_PFIFO_RAMRO 0x00002218
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#define NV40_PFIFO_RAMFC 0x00002220
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#define NV03_PFIFO_CACHES 0x00002500
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#define NV04_PFIFO_MODE 0x00002504
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#define NV04_PFIFO_DMA 0x00002508
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#define NV04_PFIFO_SIZE 0x0000250c
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#define NV03_PFIFO_CACHE0_PUSH0 0x00003000
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#define NV03_PFIFO_CACHE0_PULL0 0x00003040
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#define NV04_PFIFO_CACHE0_PULL0 0x00003050
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#define NV04_PFIFO_CACHE0_PULL1 0x00003054
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#define NV03_PFIFO_CACHE1_PUSH0 0x00003200
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#define NV03_PFIFO_CACHE1_PUSH1 0x00003204
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#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220
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#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0
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# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8
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# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000
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# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000
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# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000
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# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000
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# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000
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# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000
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# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000
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# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000
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# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000
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# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000
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# define NV_PFIFO_CACHE1_ENDIAN 0x80000000
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# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF
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# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000
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#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228
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#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c
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#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230
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#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240
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#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244
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#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248
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#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C
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#define NV03_PFIFO_CACHE1_PULL0 0x00003240
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#define NV04_PFIFO_CACHE1_PULL0 0x00003250
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#define NV03_PFIFO_CACHE1_PULL1 0x00003250
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#define NV04_PFIFO_CACHE1_PULL1 0x00003254
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#define NV04_PFIFO_CACHE1_HASH 0x00003258
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#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260
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#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264
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#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268
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#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C
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#define NV03_PFIFO_CACHE1_GET 0x00003270
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#define NV04_PFIFO_CACHE1_ENGINE 0x00003280
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#define NV10_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0
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#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0
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#define NV40_PFIFO_UNK32E4 0x000032E4
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#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8))
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#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8))
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#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8))
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#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8))
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#define NV_CRTC0_INTSTAT 0x00600100
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#define NV_CRTC0_INTEN 0x00600140
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#define NV_CRTC1_INTSTAT 0x00602100
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#define NV_CRTC1_INTEN 0x00602140
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# define NV_CRTC_INTR_VBLANK (1<<0)
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/* Fifo commands. These are not regs, neither masks */
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#define NV03_FIFO_CMD_JUMP 0x20000000
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#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc
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#define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK))
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/* RAMFC offsets */
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#define NV04_RAMFC_DMA_PUT 0x00
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#define NV04_RAMFC_DMA_GET 0x04
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#define NV04_RAMFC_DMA_INSTANCE 0x08
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#define NV04_RAMFC_DMA_FETCH 0x10
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#define NV10_RAMFC_DMA_PUT 0x00
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#define NV10_RAMFC_DMA_GET 0x04
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#define NV10_RAMFC_REF_CNT 0x08
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#define NV10_RAMFC_DMA_INSTANCE 0x0C
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#define NV10_RAMFC_DMA_STATE 0x10
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#define NV10_RAMFC_DMA_FETCH 0x14
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#define NV10_RAMFC_ENGINE 0x18
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#define NV10_RAMFC_PULL1_ENGINE 0x1C
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#define NV10_RAMFC_ACQUIRE_VALUE 0x20
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#define NV10_RAMFC_ACQUIRE_TIMESTAMP 0x24
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#define NV10_RAMFC_ACQUIRE_TIMEOUT 0x28
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#define NV10_RAMFC_SEMAPHORE 0x2C
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#define NV10_RAMFC_DMA_SUBROUTINE 0x30
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#define NV40_RAMFC_DMA_PUT 0x00
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#define NV40_RAMFC_DMA_GET 0x04
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#define NV40_RAMFC_REF_CNT 0x08
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#define NV40_RAMFC_DMA_INSTANCE 0x0C
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#define NV40_RAMFC_DMA_DCOUNT /* ? */ 0x10
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#define NV40_RAMFC_DMA_STATE 0x14
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#define NV40_RAMFC_DMA_FETCH 0x18
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#define NV40_RAMFC_ENGINE 0x1C
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#define NV40_RAMFC_PULL1_ENGINE 0x20
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#define NV40_RAMFC_ACQUIRE_VALUE 0x24
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#define NV40_RAMFC_ACQUIRE_TIMESTAMP 0x28
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#define NV40_RAMFC_ACQUIRE_TIMEOUT 0x2C
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#define NV40_RAMFC_SEMAPHORE 0x30
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#define NV40_RAMFC_DMA_SUBROUTINE 0x34
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#define NV40_RAMFC_GRCTX_INSTANCE /* guess */ 0x38
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#define NV40_RAMFC_DMA_TIMESLICE 0x3C
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#define NV40_RAMFC_UNK_40 0x40
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#define NV40_RAMFC_UNK_44 0x44
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#define NV40_RAMFC_UNK_48 0x48
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#define NV40_RAMFC_UNK_4C 0x4C
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#define NV40_RAMFC_UNK_50 0x50
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