616 lines
16 KiB
C
616 lines
16 KiB
C
/*
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* Copyright (C) 2006 Ben Skeggs.
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*
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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/*
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* Authors:
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* Ben Skeggs <darktama@iinet.net.au>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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/* TODO
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* - Check object class, deny unsafe objects (add card-specific versioning?)
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* - Get rid of DMA object creation, this should be wrapped by MM routines.
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*/
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/* Translate a RAMIN offset into a value the card understands, will be useful
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* in the future when we can access more instance ram which isn't mapped into
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* the PRAMIN aperture
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*/
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uint32_t nouveau_chip_instance_get(drm_device_t *dev, uint32_t instance)
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{
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return (instance>>4);
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}
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static void nouveau_object_link(drm_device_t *dev, int fifo_num,
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struct nouveau_object *obj)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_fifo *fifo = &dev_priv->fifos[fifo_num];
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if (!fifo->objs) {
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fifo->objs = obj;
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return;
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}
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obj->prev = NULL;
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obj->next = fifo->objs;
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fifo->objs->prev = obj;
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fifo->objs = obj;
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}
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static void nouveau_object_unlink(drm_device_t *dev, int fifo_num,
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struct nouveau_object *obj)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_fifo *fifo = &dev_priv->fifos[fifo_num];
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if (obj->prev == NULL) {
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if (obj->next)
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obj->next->prev = NULL;
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fifo->objs = obj->next;
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} else if (obj->next == NULL) {
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if (obj->prev)
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obj->prev->next = NULL;
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} else {
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obj->prev->next = obj->next;
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obj->next->prev = obj->prev;
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}
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}
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static struct nouveau_object *
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nouveau_object_handle_find(drm_device_t *dev, int fifo_num, uint32_t handle)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_fifo *fifo = &dev_priv->fifos[fifo_num];
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struct nouveau_object *obj = fifo->objs;
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if (!handle)
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return NULL;
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DRM_DEBUG("Looking for handle 0x%08x\n", handle);
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while (obj) {
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if (obj->handle == handle)
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return obj;
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obj = obj->next;
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}
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DRM_DEBUG("...couldn't find handle\n");
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return NULL;
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}
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/* NVidia uses context objects to drive drawing operations.
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Context objects can be selected into 8 subchannels in the FIFO,
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and then used via DMA command buffers.
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A context object is referenced by a user defined handle (CARD32). The HW
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looks up graphics objects in a hash table in the instance RAM.
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An entry in the hash table consists of 2 CARD32. The first CARD32 contains
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the handle, the second one a bitfield, that contains the address of the
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object in instance RAM.
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The format of the second CARD32 seems to be:
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NV4 to NV30:
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15: 0 instance_addr >> 4
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17:16 engine (here uses 1 = graphics)
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28:24 channel id (here uses 0)
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31 valid (use 1)
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NV40:
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15: 0 instance_addr >> 4 (maybe 19-0)
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21:20 engine (here uses 1 = graphics)
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I'm unsure about the other bits, but using 0 seems to work.
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The key into the hash table depends on the object handle and channel id and
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is given as:
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*/
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static uint32_t nouveau_handle_hash(drm_device_t* dev, uint32_t handle,
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int fifo)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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uint32_t hash = 0;
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int i;
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for (i=32;i>0;i-=dev_priv->ramht_bits) {
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hash ^= (handle & ((1 << dev_priv->ramht_bits) - 1));
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handle >>= dev_priv->ramht_bits;
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}
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hash ^= fifo << (dev_priv->ramht_bits - 4);
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return hash << 3;
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}
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static int nouveau_hash_table_insert(drm_device_t* dev, int fifo,
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struct nouveau_object *obj)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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int ht_base = NV_RAMIN + dev_priv->ramht_offset;
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int ht_end = ht_base + dev_priv->ramht_size;
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int o_ofs, ofs;
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o_ofs = ofs = nouveau_handle_hash(dev, obj->handle, fifo);
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while (NV_READ(ht_base + ofs)) {
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ofs += 8;
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if (ofs == ht_end) ofs = ht_base;
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if (ofs == o_ofs) {
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DRM_ERROR("no free hash table entries\n");
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return 1;
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}
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}
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ofs += ht_base;
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DRM_DEBUG("Channel %d - Handle 0x%08x at 0x%08x\n",
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fifo, obj->handle, ofs);
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NV_WRITE(NV_RAMHT_HANDLE_OFFSET + ofs, obj->handle);
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if (dev_priv->card_type >= NV_40)
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NV_WRITE(NV_RAMHT_CONTEXT_OFFSET + ofs,
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(fifo << NV40_RAMHT_CONTEXT_CHANNEL_SHIFT) |
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(obj->engine << NV40_RAMHT_CONTEXT_ENGINE_SHIFT) |
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nouveau_chip_instance_get(dev, obj->instance)
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);
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else
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NV_WRITE(NV_RAMHT_CONTEXT_OFFSET + ofs,
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NV_RAMHT_CONTEXT_VALID |
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(fifo << NV_RAMHT_CONTEXT_CHANNEL_SHIFT) |
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(obj->engine << NV_RAMHT_CONTEXT_ENGINE_SHIFT) |
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nouveau_chip_instance_get(dev, obj->instance)
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);
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obj->ht_loc = ofs;
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return 0;
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}
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static void nouveau_hash_table_remove(drm_device_t* dev,
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struct nouveau_object *obj)
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{
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drm_nouveau_private_t *dev_priv = dev->dev_private;
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DRM_DEBUG("Remove handle 0x%08x at 0x%08x from HT\n",
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obj->handle, obj->ht_loc);
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if (obj->ht_loc) {
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DRM_DEBUG("... HT entry was: 0x%08x/0x%08x\n",
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NV_READ(obj->ht_loc), NV_READ(obj->ht_loc+4));
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NV_WRITE(obj->ht_loc , 0x00000000);
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NV_WRITE(obj->ht_loc+4, 0x00000000);
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}
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}
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static struct nouveau_object *nouveau_instance_alloc(drm_device_t* dev)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_object_store *objs=&dev_priv->objs;
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struct nouveau_object *obj;
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int instance = -1;
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int i = 0, j = 0;
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/* Allocate a block of instance RAM */
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if (!objs->free_instance) {
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DRM_ERROR("no free instance ram\n");
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return NULL;
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}
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for (i=0;i<(objs->num_instance>>5);i++) {
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if (objs->inst_bmap[i] == ~0) continue;
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for (j=0;j<32;j++) {
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if (!(objs->inst_bmap[i] & (1<<j))) {
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instance = (i<<5) + j;
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break;
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}
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}
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if (instance != -1) break;
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}
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DRM_DEBUG("alloced instance %d (slot %d/%d)\n", instance, i, j);
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/* Create object struct */
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obj = drm_calloc(1, sizeof(struct nouveau_object), DRM_MEM_DRIVER);
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if (!obj) {
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DRM_ERROR("couldn't alloc memory for object\n");
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return NULL;
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}
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obj->instance = objs->first_instance;
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obj->instance += (instance << (dev_priv->card_type >= NV_40 ? 5 : 4));
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DRM_DEBUG("instance address is 0x%08x\n", instance);
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/* Mark instance slot as used */
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objs->inst_bmap[i] |= (1 << j);
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objs->free_instance--;
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return obj;
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}
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static void nouveau_object_instance_free(drm_device_t *dev,
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struct nouveau_object *obj)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_object_store *objs=&dev_priv->objs;
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int count, i;
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uint32_t be, bb;
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if (dev_priv->card_type >= NV_40)
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count = 8;
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else
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count = 4;
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/* Clean RAMIN entry */
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DRM_DEBUG("Instance entry for 0x%08x"
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"(engine %d, class 0x%x) before destroy:\n",
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obj->handle, obj->engine, obj->class);
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for (i=0;i<count;i++) {
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DRM_DEBUG(" +0x%02x: 0x%08x\n", (i*4),
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INSTANCE_RD(obj->instance, i));
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INSTANCE_WR(obj->instance, i, 0x00000000);
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}
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/* Mark instance as free */
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obj->instance -= objs->first_instance;
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obj->instance >>= (dev_priv->card_type >=NV_40 ? 5 : 4);
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be = obj->instance / 32;
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bb = obj->instance % 32;
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objs->inst_bmap[be] &= ~(1<<bb);
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objs->free_instance++;
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}
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int nouveau_object_init(drm_device_t* dev)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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dev_priv->objs.first_instance =
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dev_priv->ramfc_offset +dev_priv->ramfc_size;
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dev_priv->objs.free_instance = 1024; /*FIXME*/
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dev_priv->objs.num_instance = 1024; /*FIXME*/
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dev_priv->objs.inst_bmap = drm_calloc
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(1, dev_priv->objs.num_instance/32, DRM_MEM_DRIVER);
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return 0;
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}
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/*
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DMA objects are used to reference a piece of memory in the
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framebuffer, PCI or AGP address space. Each object is 16 bytes big
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and looks as follows:
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entry[0]
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11:0 class (seems like I can always use 0 here)
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12 page table present?
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13 page entry linear?
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15:14 access: 0 rw, 1 ro, 2 wo
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17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
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31:20 dma adjust (bits 0-11 of the address)
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entry[1]
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dma limit
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entry[2]
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1 0 readonly, 1 readwrite
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31:12 dma frame address (bits 12-31 of the address)
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Non linear page tables seem to need a list of frame addresses afterwards,
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the rivatv project has some info on this.
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The method below creates a DMA object in instance RAM and returns a handle
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to it that can be used to set up context objects.
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*/
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struct nouveau_object *nouveau_dma_object_create(drm_device_t* dev,
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uint32_t offset, uint32_t size,
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int access, uint32_t target)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_object *obj;
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uint32_t frame, adjust;
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DRM_DEBUG("offset:0x%08x, size:0x%08x, target:%d, access:%d\n",
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offset, size, target, access);
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frame = offset & ~0x00000FFF;
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adjust = offset & 0x00000FFF;
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obj = nouveau_instance_alloc(dev);
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if (!obj) {
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DRM_ERROR("couldn't allocate DMA object\n");
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return obj;
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}
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obj->engine = 0;
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obj->class = 0;
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INSTANCE_WR(obj->instance, 0, ((1<<12) | (1<<13) |
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(adjust << 20) |
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(access << 14) |
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(target << 16) |
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0x3D /* DMA_IN_MEMORY */));
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INSTANCE_WR(obj->instance, 1, size-1);
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INSTANCE_WR(obj->instance, 2,
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frame | ((access != NV_DMA_ACCESS_RO) ? (1<<1) : 0));
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/* I don't actually know what this is, the DMA objects I see
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* in renouveau dumps usually have this as the same as +8
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*/
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INSTANCE_WR(obj->instance, 3,
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frame | ((access != NV_DMA_ACCESS_RO) ? (1<<1) : 0));
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return obj;
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}
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/* Context objects in the instance RAM have the following structure.
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* On NV40 they are 32 byte long, on NV30 and smaller 16 bytes.
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NV4 - NV30:
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entry[0]
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11:0 class
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12 chroma key enable
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13 user clip enable
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14 swizzle enable
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17:15 patch config:
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scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre
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18 synchronize enable
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19 endian: 1 big, 0 little
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21:20 dither mode
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23 single step enable
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24 patch status: 0 invalid, 1 valid
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25 context_surface 0: 1 valid
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26 context surface 1: 1 valid
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27 context pattern: 1 valid
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28 context rop: 1 valid
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29,30 context beta, beta4
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entry[1]
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7:0 mono format
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15:8 color format
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31:16 notify instance address
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entry[2]
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15:0 dma 0 instance address
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31:16 dma 1 instance address
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entry[3]
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dma method traps
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NV40:
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No idea what the exact format is. Here's what can be deducted:
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entry[0]:
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11:0 class (maybe uses more bits here?)
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17 user clip enable
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21:19 patch config
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25 patch status valid ?
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entry[1]:
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15:0 DMA notifier (maybe 20:0)
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entry[2]:
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15:0 DMA 0 instance (maybe 20:0)
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24 big endian
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entry[3]:
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15:0 DMA 1 instance (maybe 20:0)
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entry[4]:
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entry[5]:
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set to 0?
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*/
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static struct nouveau_object *nouveau_context_object_create(drm_device_t* dev,
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int class, uint32_t flags,
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struct nouveau_object *dma0,
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struct nouveau_object *dma1,
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struct nouveau_object *dma_notifier)
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{
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drm_nouveau_private_t *dev_priv=dev->dev_private;
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struct nouveau_object *obj;
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uint32_t d0, d1, dn;
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uint32_t flags0,flags1,flags2;
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flags0=0;flags1=0;flags2=0;
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if (dev_priv->card_type >= NV_40) {
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if (flags & NV_DMA_CONTEXT_FLAGS_PATCH_ROP_AND)
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flags0 |= 0x02080000;
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else if (flags & NV_DMA_CONTEXT_FLAGS_PATCH_SRCCOPY)
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flags0 |= 0x02080000;
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if (flags & NV_DMA_CONTEXT_FLAGS_CLIP_ENABLE)
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flags0 |= 0x00020000;
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#ifdef __BIG_ENDIAN
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if (flags & NV_DMA_CONTEXT_FLAGS_MONO)
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flags1 |= 0x01000000;
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flags2 |= 0x01000000;
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#else
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if (flags & NV_DMA_CONTEXT_FLAGS_MONO)
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flags1 |= 0x02000000;
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#endif
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} else {
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if (flags & NV_DMA_CONTEXT_FLAGS_PATCH_ROP_AND)
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flags0 |= 0x01008000;
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else if (flags & NV_DMA_CONTEXT_FLAGS_PATCH_SRCCOPY)
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flags0 |= 0x01018000;
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if (flags & NV_DMA_CONTEXT_FLAGS_CLIP_ENABLE)
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flags0 |= 0x00002000;
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#ifdef __BIG_ENDIAN
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flags0 |= 0x00080000;
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if (flags & NV_DMA_CONTEXT_FLAGS_MONO)
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flags1 |= 0x00000001;
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#else
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if (flags & NV_DMA_CONTEXT_FLAGS_MONO)
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flags1 |= 0x00000002;
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#endif
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}
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DRM_DEBUG("class=%x, dma0=%08x, dma1=%08x, dman=%08x\n",
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class,
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dma0 ? dma0->handle : 0,
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dma1 ? dma1->handle : 0,
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dma_notifier ? dma_notifier->handle : 0);
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obj = nouveau_instance_alloc(dev);
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if (!obj) {
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DRM_ERROR("couldn't allocate context object\n");
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return obj;
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}
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obj->engine = 1;
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obj->class = class;
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d0 = dma0 ? nouveau_chip_instance_get(dev, dma0->instance) : 0;
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d1 = dma1 ? nouveau_chip_instance_get(dev, dma1->instance) : 0;
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dn = dma_notifier ?
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nouveau_chip_instance_get(dev, dma_notifier->instance) : 0;
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if (dev_priv->card_type >= NV_40) {
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INSTANCE_WR(obj->instance, 0, class | flags0);
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INSTANCE_WR(obj->instance, 1, dn | flags1);
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INSTANCE_WR(obj->instance, 2, d0 | flags2);
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INSTANCE_WR(obj->instance, 3, d1);
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INSTANCE_WR(obj->instance, 4, 0x00000000);
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INSTANCE_WR(obj->instance, 5, 0x00000000);
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INSTANCE_WR(obj->instance, 6, 0x00000000);
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INSTANCE_WR(obj->instance, 7, 0x00000000);
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} else {
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INSTANCE_WR(obj->instance, 0, class | flags0);
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INSTANCE_WR(obj->instance, 1, (dn << 16) | flags1);
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INSTANCE_WR(obj->instance, 2, d0 | (d1 << 16));
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INSTANCE_WR(obj->instance, 3, 0);
|
|
}
|
|
|
|
return obj;
|
|
}
|
|
|
|
static void
|
|
nouveau_object_free(drm_device_t *dev, int fifo_num, struct nouveau_object *obj)
|
|
{
|
|
nouveau_object_unlink(dev, fifo_num, obj);
|
|
|
|
nouveau_object_instance_free(dev, obj);
|
|
nouveau_hash_table_remove(dev, obj);
|
|
|
|
drm_free(obj, sizeof(struct nouveau_object), DRM_MEM_DRIVER);
|
|
return;
|
|
}
|
|
|
|
void nouveau_object_cleanup(drm_device_t *dev, DRMFILE filp)
|
|
{
|
|
drm_nouveau_private_t *dev_priv=dev->dev_private;
|
|
int fifo;
|
|
|
|
fifo = nouveau_fifo_id_get(dev, filp);
|
|
if (fifo == -1)
|
|
return;
|
|
|
|
while (dev_priv->fifos[fifo].objs)
|
|
nouveau_object_free(dev, fifo, dev_priv->fifos[fifo].objs);
|
|
}
|
|
|
|
int nouveau_ioctl_object_init(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
drm_nouveau_object_init_t init;
|
|
struct nouveau_object *obj, *dma0, *dma1, *dman;
|
|
int fifo;
|
|
|
|
fifo = nouveau_fifo_id_get(dev, filp);
|
|
if (fifo == -1)
|
|
return DRM_ERR(EINVAL);
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_object_init_t __user *)
|
|
data, sizeof(init));
|
|
|
|
//FIXME: check args, only allow trusted objects to be created
|
|
|
|
if (nouveau_object_handle_find(dev, fifo, init.handle)) {
|
|
DRM_ERROR("Channel %d: handle 0x%08x already exists\n",
|
|
fifo, init.handle);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
dma0 = nouveau_object_handle_find(dev, fifo, init.dma0);
|
|
if (init.dma0 && !dma0) {
|
|
DRM_ERROR("context dma0 - invalid handle 0x%08x\n", init.dma0);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
dma1 = nouveau_object_handle_find(dev, fifo, init.dma1);
|
|
if (init.dma1 && !dma1) {
|
|
DRM_ERROR("context dma1 - invalid handle 0x%08x\n", init.dma0);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
dman = nouveau_object_handle_find(dev, fifo, init.dma_notifier);
|
|
if (init.dma_notifier && !dman) {
|
|
DRM_ERROR("context dman - invalid handle 0x%08x\n",
|
|
init.dma_notifier);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
obj = nouveau_context_object_create(dev, init.class, init.flags,
|
|
dma0, dma1, dman);
|
|
if (!obj)
|
|
return DRM_ERR(ENOMEM);
|
|
|
|
obj->handle = init.handle;
|
|
|
|
if (nouveau_hash_table_insert(dev, fifo, obj)) {
|
|
nouveau_object_free(dev, fifo, obj);
|
|
return DRM_ERR(ENOMEM);
|
|
}
|
|
|
|
nouveau_object_link(dev, fifo, obj);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int nouveau_ioctl_dma_object_init(DRM_IOCTL_ARGS)
|
|
{
|
|
DRM_DEVICE;
|
|
drm_nouveau_dma_object_init_t init;
|
|
struct nouveau_object *obj;
|
|
int fifo;
|
|
|
|
fifo = nouveau_fifo_id_get(dev, filp);
|
|
if (fifo == -1)
|
|
return DRM_ERR(EINVAL);
|
|
|
|
DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_dma_object_init_t __user *)
|
|
data, sizeof(init));
|
|
|
|
if (nouveau_object_handle_find(dev, fifo, init.handle)) {
|
|
DRM_ERROR("Channel %d: handle 0x%08x already exists\n",
|
|
fifo, init.handle);
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
|
|
obj = nouveau_dma_object_create(dev, init.offset, init.size,
|
|
init.access, init.target);
|
|
if (!obj)
|
|
return DRM_ERR(ENOMEM);
|
|
|
|
obj->handle = init.handle;
|
|
if (nouveau_hash_table_insert(dev, fifo, obj)) {
|
|
nouveau_object_free(dev, fifo, obj);
|
|
return DRM_ERR(ENOMEM);
|
|
}
|
|
|
|
nouveau_object_link(dev, fifo, obj);
|
|
|
|
return 0;
|
|
}
|
|
|