463 lines
16 KiB
C
463 lines
16 KiB
C
/*
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* Copyright 2007-8 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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*/
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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#include "drm_crtc_helper.h"
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#include "atom.h"
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#include "atom-bits.h"
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static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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int index = GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
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ENABLE_CRTC_PS_ALLOCATION args;
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memset(&args, 0, sizeof(args));
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args.ucCRTC = radeon_crtc->crtc_id;
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args.ucEnable = lock;
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atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
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}
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static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
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ENABLE_CRTC_PS_ALLOCATION args;
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memset(&args, 0, sizeof(args));
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args.ucCRTC = radeon_crtc->crtc_id;
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args.ucEnable = state;
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atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
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}
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static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
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ENABLE_CRTC_PS_ALLOCATION args;
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memset(&args, 0, sizeof(args));
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args.ucCRTC = radeon_crtc->crtc_id;
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args.ucEnable = state;
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atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
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}
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static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
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BLANK_CRTC_PS_ALLOCATION args;
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memset(&args, 0, sizeof(args));
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args.ucCRTC = radeon_crtc->crtc_id;
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args.ucBlanking = state;
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atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
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}
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void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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switch(mode) {
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case DRM_MODE_DPMS_ON:
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case DRM_MODE_DPMS_STANDBY:
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case DRM_MODE_DPMS_SUSPEND:
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if (radeon_is_dce3(dev_priv))
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atombios_enable_crtc_memreq(crtc, 1);
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atombios_enable_crtc(crtc, 1);
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atombios_blank_crtc(crtc, 0);
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radeon_crtc_load_lut(crtc);
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break;
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case DRM_MODE_DPMS_OFF:
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atombios_blank_crtc(crtc, 1);
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atombios_enable_crtc(crtc, 0);
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if (radeon_is_dce3(dev_priv))
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atombios_enable_crtc_memreq(crtc, 0);
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break;
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}
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}
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static void
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atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, SET_CRTC_USING_DTD_TIMING_PARAMETERS *crtc_param)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param;
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int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
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conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size);
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conv_param.usH_Blanking_Time = cpu_to_le16(crtc_param->usH_Blanking_Time);
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conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size);
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conv_param.usV_Blanking_Time = cpu_to_le16(crtc_param->usV_Blanking_Time);
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conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset);
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conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
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conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset);
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conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
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conv_param.susModeMiscInfo.usAccess = cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
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conv_param.ucCRTC = crtc_param->ucCRTC;
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printk("executing set crtc dtd timing\n");
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atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&conv_param);
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}
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void atombios_crtc_set_timing(struct drm_crtc *crtc, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
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int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
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conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total);
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conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp);
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conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart);
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conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
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conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total);
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conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp);
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conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart);
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conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
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conv_param.susModeMiscInfo.usAccess = cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
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conv_param.ucCRTC = crtc_param->ucCRTC;
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conv_param.ucOverscanRight = crtc_param->ucOverscanRight;
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conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft;
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conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom;
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conv_param.ucOverscanTop = crtc_param->ucOverscanTop;
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conv_param.ucReserved = crtc_param->ucReserved;
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printk("executing set crtc timing\n");
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atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&conv_param);
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}
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void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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uint8_t frev, crev;
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int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
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SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
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PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
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PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
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uint32_t sclock = mode->clock;
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uint32_t ref_div = 0, fb_div = 0, post_div = 0;
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struct radeon_pll *pll;
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int pll_flags = 0;
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memset(&spc_param, 0, sizeof(SET_PIXEL_CLOCK_PS_ALLOCATION));
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if (!radeon_is_avivo(dev_priv))
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pll_flags |= RADEON_PLL_LEGACY;
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if (mode->clock > 200000) /* range limits??? */
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pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
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else
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pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
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if (radeon_crtc->crtc_id == 0)
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pll = &dev_priv->mode_info.p1pll;
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else
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pll = &dev_priv->mode_info.p2pll;
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radeon_compute_pll(pll, mode->clock, &sclock,
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&fb_div, &ref_div, &post_div, pll_flags);
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if (radeon_is_avivo(dev_priv)) {
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uint32_t ss_cntl;
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if (radeon_crtc->crtc_id == 0) {
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ss_cntl = RADEON_READ(AVIVO_P1PLL_INT_SS_CNTL);
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RADEON_WRITE(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
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} else {
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ss_cntl = RADEON_READ(AVIVO_P2PLL_INT_SS_CNTL);
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RADEON_WRITE(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
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}
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}
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/* */
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atom_parse_cmd_header(dev_priv->mode_info.atom_context, index, &frev, &crev);
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switch(frev) {
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case 1:
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switch(crev) {
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case 1:
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case 2:
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spc2_ptr = (PIXEL_CLOCK_PARAMETERS_V2*)&spc_param.sPCLKInput;
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spc2_ptr->usPixelClock = cpu_to_le16(sclock);
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spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
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spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
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spc2_ptr->ucPostDiv = post_div;
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spc2_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
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spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
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spc2_ptr->ucRefDivSrc = 1;
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break;
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case 3:
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spc3_ptr = (PIXEL_CLOCK_PARAMETERS_V3*)&spc_param.sPCLKInput;
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spc3_ptr->usPixelClock = cpu_to_le16(sclock);
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spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
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spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
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spc3_ptr->ucPostDiv = post_div;
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spc3_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
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spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
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/* TODO insert output encoder object stuff herre for r600 */
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break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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return;
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}
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break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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return;
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}
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printk("executing set pll\n");
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atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&spc_param);
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}
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void atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_framebuffer *radeon_fb;
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struct drm_gem_object *obj;
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struct drm_radeon_gem_object *obj_priv;
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uint32_t fb_location, fb_format, fb_pitch_pixels;
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if (!crtc->fb)
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return;
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radeon_fb = to_radeon_framebuffer(crtc->fb);
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obj = radeon_fb->obj;
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obj_priv = obj->driver_private;
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fb_location = obj_priv->bo->offset + dev_priv->fb_location;
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switch(crtc->fb->bits_per_pixel) {
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case 15:
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fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
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break;
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case 16:
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fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
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break;
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case 24:
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case 32:
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fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
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break;
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default:
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DRM_ERROR("Unsupported screen depth %d\n", crtc->fb->bits_per_pixel);
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return;
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}
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/* TODO tiling */
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if (radeon_crtc->crtc_id == 0)
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RADEON_WRITE(AVIVO_D1VGA_CONTROL, 0);
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else
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RADEON_WRITE(AVIVO_D2VGA_CONTROL, 0);
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RADEON_WRITE(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
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RADEON_WRITE(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
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RADEON_WRITE(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
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RADEON_WRITE(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
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RADEON_WRITE(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
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RADEON_WRITE(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, x);
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RADEON_WRITE(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, y);
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RADEON_WRITE(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, x + crtc->mode.hdisplay);
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RADEON_WRITE(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, y + crtc->mode.vdisplay);
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fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
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RADEON_WRITE(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
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RADEON_WRITE(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
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RADEON_WRITE(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
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crtc->mode.vdisplay);
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RADEON_WRITE(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
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RADEON_WRITE(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
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(crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
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if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
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RADEON_WRITE(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
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AVIVO_D1MODE_INTERLEAVE_EN);
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else
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RADEON_WRITE(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
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0);
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}
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void atombios_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct drm_encoder *encoder;
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SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
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/* TODO color tiling */
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memset(&crtc_timing, 0, sizeof(crtc_timing));
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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}
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crtc_timing.ucCRTC = radeon_crtc->crtc_id;
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crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
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crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
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crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
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crtc_timing.usH_SyncWidth = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
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crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
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crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
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crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
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crtc_timing.usV_SyncWidth = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
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if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
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crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
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if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
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crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
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if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
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crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
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if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
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crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
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atombios_crtc_set_pll(crtc, adjusted_mode);
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atombios_crtc_set_timing(crtc, &crtc_timing);
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if (radeon_is_avivo(dev_priv))
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atombios_crtc_set_base(crtc, x, y);
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else {
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if (radeon_crtc->crtc_id == 0) {
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SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing;
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memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing));
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|
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/* setup FP shadow regs on R4xx */
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crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id;
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crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay;
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crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay;
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crtc_dtd_timing.usH_Blanking_Time = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hdisplay;
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crtc_dtd_timing.usV_Blanking_Time = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vdisplay;
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crtc_dtd_timing.usH_SyncOffset = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
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crtc_dtd_timing.usV_SyncOffset = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
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crtc_dtd_timing.usH_SyncWidth = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
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crtc_dtd_timing.usV_SyncWidth = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
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//crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder;
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//crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder;
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|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
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crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
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|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
|
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crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
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|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
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crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
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|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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|
crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
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|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
|
crtc_dtd_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
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|
|
|
atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing);
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}
|
|
radeon_crtc_set_base(crtc, x, y);
|
|
radeon_legacy_atom_set_surface(crtc);
|
|
}
|
|
|
|
}
|
|
|
|
static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
|
|
struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
|
|
static void atombios_crtc_prepare(struct drm_crtc *crtc)
|
|
{
|
|
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
|
|
atombios_lock_crtc(crtc, 1);
|
|
}
|
|
|
|
static void atombios_crtc_commit(struct drm_crtc *crtc)
|
|
{
|
|
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
|
|
atombios_lock_crtc(crtc, 0);
|
|
}
|
|
|
|
static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
|
|
.dpms = atombios_crtc_dpms,
|
|
.mode_fixup = atombios_crtc_mode_fixup,
|
|
.mode_set = atombios_crtc_mode_set,
|
|
.mode_set_base = atombios_crtc_set_base,
|
|
.prepare = atombios_crtc_prepare,
|
|
.commit = atombios_crtc_commit,
|
|
};
|
|
|
|
void radeon_atombios_init_crtc(struct drm_device *dev,
|
|
struct radeon_crtc *radeon_crtc)
|
|
{
|
|
if (radeon_crtc->crtc_id == 1)
|
|
radeon_crtc->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
|
|
drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
|
|
}
|