366 lines
13 KiB
C
366 lines
13 KiB
C
/*
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* Copyright 2007-8 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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*/
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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#include "atom.h"
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#include "atom-bits.h"
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union atom_supported_devices {
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struct _ATOM_SUPPORTED_DEVICES_INFO info;
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struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
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struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
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};
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static inline struct radeon_i2c_bus_rec radeon_lookup_gpio_for_ddc(struct drm_device *dev, uint8_t id)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct atom_context *ctx = dev_priv->mode_info.atom_context;
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ATOM_GPIO_I2C_ASSIGMENT gpio;
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struct radeon_i2c_bus_rec i2c;
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int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
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struct _ATOM_GPIO_I2C_INFO *i2c_info;
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uint16_t data_offset;
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memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
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i2c.valid = false;
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atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
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i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
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gpio = i2c_info->asGPIO_Info[id];
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i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
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i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
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i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
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i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
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i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
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i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
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i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
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i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
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i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
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i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
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i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
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i2c.put_data_mask = (1 << gpio.ucDataEnShift);
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i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
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i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
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i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
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i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
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i2c.valid = true;
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return i2c;
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}
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static void radeon_atom_apply_quirks(struct drm_device *dev, int index)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_mode_info *mode_info = &dev_priv->mode_info;
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if ((dev->pdev->device == 0x791e) &&
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(dev->pdev->subsystem_vendor == 0x1043) &&
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(dev->pdev->subsystem_device == 0x826d)) {
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if ((mode_info->bios_connector[index].connector_type == CONNECTOR_HDMI_TYPE_A) &&
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(mode_info->bios_connector[index].tmds_type == TMDS_LVTMA)) {
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mode_info->bios_connector[index].connector_type = CONNECTOR_DVI_D;
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}
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}
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if ((dev->pdev->device == 0x5653) &&
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(dev->pdev->subsystem_vendor == 0x1462) &&
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(dev->pdev->subsystem_device == 0x0291)) {
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if (mode_info->bios_connector[index].connector_type == CONNECTOR_LVDS) {
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mode_info->bios_connector[index].ddc_i2c.valid = false;
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}
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}
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}
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bool radeon_get_atom_connector_info_from_bios_connector_table(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_mode_info *mode_info = &dev_priv->mode_info;
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struct atom_context *ctx = mode_info->atom_context;
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int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
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uint16_t size, data_offset;
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uint8_t frev, crev;
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uint16_t device_support;
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union atom_supported_devices *supported_devices;
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int i,j;
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atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
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supported_devices = (union atom_supported_devices *)(ctx->bios + data_offset);
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device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
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for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
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ATOM_CONNECTOR_INFO_I2C ci = supported_devices->info.asConnInfo[i];
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if (!(device_support & (1 << i))) {
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mode_info->bios_connector[i].valid = false;
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continue;
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}
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if (i == ATOM_DEVICE_CV_INDEX) {
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DRM_DEBUG("Skipping Component Video\n");
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mode_info->bios_connector[i].valid = false;
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continue;
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}
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if (i == ATOM_DEVICE_TV1_INDEX) {
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DRM_DEBUG("Skipping TV Out\n");
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mode_info->bios_connector[i].valid = false;
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continue;
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}
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mode_info->bios_connector[i].valid = true;
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mode_info->bios_connector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux;
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mode_info->bios_connector[i].devices = 1 << i;
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mode_info->bios_connector[i].connector_type = ci.sucConnectorInfo.sbfAccess.bfConnectorType;
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if (mode_info->bios_connector[i].connector_type == CONNECTOR_NONE) {
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mode_info->bios_connector[i].valid = false;
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continue;
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}
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mode_info->bios_connector[i].dac_type = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
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if ((i == ATOM_DEVICE_TV1_INDEX) ||
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(i == ATOM_DEVICE_TV2_INDEX) ||
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(i == ATOM_DEVICE_TV1_INDEX))
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mode_info->bios_connector[i].ddc_i2c.valid = false;
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else if ((dev_priv->chip_family == CHIP_RS600) ||
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(dev_priv->chip_family == CHIP_RS690) ||
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(dev_priv->chip_family == CHIP_RS740)) {
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if ((i == ATOM_DEVICE_DFP2_INDEX) || (i == ATOM_DEVICE_DFP3_INDEX))
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mode_info->bios_connector[i].ddc_i2c =
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radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
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else
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mode_info->bios_connector[i].ddc_i2c =
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radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
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} else
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mode_info->bios_connector[i].ddc_i2c =
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radeon_lookup_gpio_for_ddc(dev, ci.sucI2cId.sbfAccess.bfI2C_LineMux);
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if (i == ATOM_DEVICE_DFP1_INDEX)
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mode_info->bios_connector[i].tmds_type = TMDS_INT;
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else if (i == ATOM_DEVICE_DFP2_INDEX) {
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if ((dev_priv->chip_family == CHIP_RS600) ||
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(dev_priv->chip_family == CHIP_RS690) ||
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(dev_priv->chip_family == CHIP_RS740))
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mode_info->bios_connector[i].tmds_type = TMDS_DDIA;
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else
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mode_info->bios_connector[i].tmds_type = TMDS_EXT;
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} else if (i == ATOM_DEVICE_DFP3_INDEX)
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mode_info->bios_connector[i].tmds_type = TMDS_LVTMA;
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else
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mode_info->bios_connector[i].tmds_type = TMDS_NONE;
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/* Always set the connector type to VGA for CRT1/CRT2. if they are
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* shared with a DVI port, we'll pick up the DVI connector below when we
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* merge the outputs
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*/
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if ((i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) &&
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(mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_I ||
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mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_D ||
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mode_info->bios_connector[i].connector_type == CONNECTOR_DVI_A)) {
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mode_info->bios_connector[i].connector_type = CONNECTOR_VGA;
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}
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if (crev > 1) {
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ATOM_CONNECTOR_INC_SRC_BITMAP isb = supported_devices->info_2.asIntSrcInfo[i];
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switch(isb.ucIntSrcBitmap) {
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case 0x4:
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mode_info->bios_connector[i].hpd_mask = 0x1;
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break;
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case 0xa:
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mode_info->bios_connector[i].hpd_mask = 0x100;
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break;
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default:
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mode_info->bios_connector[i].hpd_mask = 0;
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break;
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}
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} else {
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mode_info->bios_connector[i].hpd_mask = 0;
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}
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radeon_atom_apply_quirks(dev, i);
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}
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/* CRTs/DFPs may share a port */
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for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
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if (!mode_info->bios_connector[i].valid)
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continue;
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for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
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if (mode_info->bios_connector[j].valid && (i != j)) {
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if (mode_info->bios_connector[i].output_id ==
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mode_info->bios_connector[j].output_id) {
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if (((i == ATOM_DEVICE_DFP1_INDEX) ||
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(i == ATOM_DEVICE_DFP2_INDEX) ||
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(i == ATOM_DEVICE_DFP3_INDEX)) &&
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((j == ATOM_DEVICE_CRT1_INDEX) ||
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(j == ATOM_DEVICE_CRT2_INDEX))) {
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mode_info->bios_connector[i].dac_type = mode_info->bios_connector[j].dac_type;
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mode_info->bios_connector[i].devices |= mode_info->bios_connector[j].devices;
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mode_info->bios_connector[i].hpd_mask = mode_info->bios_connector[j].hpd_mask;
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mode_info->bios_connector[j].valid = false;
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} else if (((j == ATOM_DEVICE_DFP1_INDEX) ||
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(j == ATOM_DEVICE_DFP2_INDEX) ||
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(j == ATOM_DEVICE_DFP3_INDEX)) &&
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((i == ATOM_DEVICE_CRT1_INDEX) ||
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(i == ATOM_DEVICE_CRT2_INDEX))) {
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mode_info->bios_connector[j].dac_type = mode_info->bios_connector[i].dac_type;
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mode_info->bios_connector[j].devices |= mode_info->bios_connector[i].devices;
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mode_info->bios_connector[j].hpd_mask = mode_info->bios_connector[i].hpd_mask;
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mode_info->bios_connector[i].valid = false;
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}
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}
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}
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}
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}
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DRM_DEBUG("BIOS Connector table\n");
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for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
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if (!mode_info->bios_connector[i].valid)
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continue;
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DRM_DEBUG("Port %d: ddc_type 0x%x, dac_type %d, tmds_type %d, connector type %d, hpd_mask %d\n",
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i, mode_info->bios_connector[i].ddc_i2c.mask_clk_reg,
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mode_info->bios_connector[i].dac_type,
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mode_info->bios_connector[i].tmds_type,
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mode_info->bios_connector[i].connector_type,
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mode_info->bios_connector[i].hpd_mask);
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}
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return true;
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}
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union firmware_info {
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ATOM_FIRMWARE_INFO info;
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ATOM_FIRMWARE_INFO_V1_2 info_12;
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ATOM_FIRMWARE_INFO_V1_3 info_13;
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ATOM_FIRMWARE_INFO_V1_4 info_14;
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};
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bool radeon_atom_get_clock_info(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_mode_info *mode_info = &dev_priv->mode_info;
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int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
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union firmware_info *firmware_info;
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uint8_t frev, crev;
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struct radeon_pll *pll = &mode_info->pll;
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uint16_t data_offset;
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atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
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firmware_info = (union firmware_info *)(mode_info->atom_context->bios + data_offset);
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pll->reference_freq = le16_to_cpu(firmware_info->info.usReferenceClock);
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pll->reference_div = 0;
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pll->pll_out_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
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pll->pll_out_max = le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
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if (pll->pll_out_min == 0) {
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if (radeon_is_avivo(dev_priv))
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pll->pll_out_min = 64800;
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else
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pll->pll_out_min = 20000;
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}
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pll->pll_in_min = le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
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pll->pll_in_max = le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
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pll->xclk = le16_to_cpu(firmware_info->info.usMaxPixelClock);
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return true;
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}
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union lvds_info {
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struct _ATOM_LVDS_INFO info;
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struct _ATOM_LVDS_INFO_V12 info_12;
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};
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void radeon_get_lvds_info(struct radeon_encoder *encoder)
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{
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struct drm_device *dev = encoder->base.dev;
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_mode_info *mode_info = &dev_priv->mode_info;
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int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
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uint16_t data_offset;
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union lvds_info *lvds_info;
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uint8_t frev, crev;
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atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
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lvds_info = (union lvds_info *)(mode_info->atom_context->bios + data_offset);
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encoder->dotclock = le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
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encoder->panel_xres = le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
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encoder->panel_yres = le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
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encoder->hblank = le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
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encoder->hoverplus = le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
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encoder->hsync_width = le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
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encoder->vblank = le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
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encoder->hoverplus = le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
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encoder->hsync_width = le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
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encoder->panel_pwr_delay = le16_to_cpu(lvds_info->info.usOffDelayInMs);
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}
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void radeon_atom_dyn_clk_setup(struct drm_device *dev, int enable)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_mode_info *mode_info = &dev_priv->mode_info;
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struct atom_context *ctx = mode_info->atom_context;
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DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
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int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
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args.ucEnable = enable;
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atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
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}
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void radeon_atom_static_pwrmgt_setup(struct drm_device *dev, int enable)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_mode_info *mode_info = &dev_priv->mode_info;
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struct atom_context *ctx = mode_info->atom_context;
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ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
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int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
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args.ucEnable = enable;
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atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
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}
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