926 lines
29 KiB
C
926 lines
29 KiB
C
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
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*/
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/*
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _I915_DRV_H_
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#define _I915_DRV_H_
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/* General customization:
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*/
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#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
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#define DRIVER_NAME "i915"
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#define DRIVER_DESC "Intel Graphics"
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#define DRIVER_DATE "20070209"
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/* Interface history:
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*
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* 1.1: Original.
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* 1.2: Add Power Management
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* 1.3: Add vblank support
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* 1.4: Fix cmdbuffer path, add heap destroy
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* 1.5: Add vblank pipe configuration
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* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
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* - Support vertical blank on secondary display pipe
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* 1.8: New ioctl for ARB_Occlusion_Query
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* 1.9: Usable page flipping and triple buffering
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*/
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 9
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#define DRIVER_PATCHLEVEL 0
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#if defined(__linux__)
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#define I915_HAVE_FENCE
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#define I915_HAVE_BUFFER
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#endif
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typedef struct _drm_i915_ring_buffer {
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int tail_mask;
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unsigned long Start;
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unsigned long End;
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unsigned long Size;
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u8 *virtual_start;
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int head;
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int tail;
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int space;
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drm_local_map_t map;
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} drm_i915_ring_buffer_t;
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struct mem_block {
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struct mem_block *next;
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struct mem_block *prev;
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int start;
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int size;
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DRMFILE filp; /* 0: free, -1: heap, other: real files */
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};
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typedef struct _drm_i915_vbl_swap {
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struct list_head head;
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drm_drawable_t drw_id;
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unsigned int pipe;
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unsigned int sequence;
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int flip;
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} drm_i915_vbl_swap_t;
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typedef struct drm_i915_private {
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drm_local_map_t *sarea;
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drm_local_map_t *mmio_map;
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unsigned long baseaddr;
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unsigned long mmiobase;
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unsigned long mmiolen;
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drm_i915_sarea_t *sarea_priv;
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drm_i915_ring_buffer_t ring;
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drm_dma_handle_t *status_page_dmah;
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void *hw_status_page;
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dma_addr_t dma_status_page;
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uint32_t counter;
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unsigned int cpp;
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int use_mi_batchbuffer_start;
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wait_queue_head_t irq_queue;
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atomic_t irq_received;
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atomic_t irq_emitted;
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int tex_lru_log_granularity;
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int allow_batchbuffer;
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struct mem_block *agp_heap;
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unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
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int vblank_pipe;
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spinlock_t user_irq_lock;
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int user_irq_refcount;
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int fence_irq_on;
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uint32_t irq_enable_reg;
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int irq_enabled;
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#ifdef I915_HAVE_FENCE
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uint32_t flush_sequence;
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uint32_t flush_flags;
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uint32_t flush_pending;
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uint32_t saved_flush_status;
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#endif
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#ifdef I915_HAVE_BUFFER
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void *agp_iomap;
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#endif
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spinlock_t swaps_lock;
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drm_i915_vbl_swap_t vbl_swaps;
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unsigned int swaps_pending;
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/* LVDS info */
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int backlight_duty_cycle; /* restore backlight to this value */
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bool panel_wants_dither;
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struct drm_display_mode *panel_fixed_mode;
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/* Register state */
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u32 saveDSPACNTR;
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u32 saveDSPBCNTR;
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u32 savePIPEACONF;
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u32 savePIPEBCONF;
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u32 savePIPEASRC;
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u32 savePIPEBSRC;
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u32 saveFPA0;
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u32 saveFPA1;
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u32 saveDPLL_A;
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u32 saveDPLL_A_MD;
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u32 saveHTOTAL_A;
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u32 saveHBLANK_A;
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u32 saveHSYNC_A;
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u32 saveVTOTAL_A;
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u32 saveVBLANK_A;
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u32 saveVSYNC_A;
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u32 saveDSPASTRIDE;
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u32 saveDSPASIZE;
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u32 saveDSPAPOS;
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u32 saveDSPABASE;
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u32 saveDSPASURF;
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u32 saveFPB0;
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u32 saveFPB1;
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u32 saveDPLL_B;
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u32 saveDPLL_B_MD;
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u32 saveHTOTAL_B;
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u32 saveHBLANK_B;
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u32 saveHSYNC_B;
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u32 saveVTOTAL_B;
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u32 saveVBLANK_B;
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u32 saveVSYNC_B;
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u32 saveDSPBSTRIDE;
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u32 saveDSPBSIZE;
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u32 saveDSPBPOS;
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u32 saveDSPBBASE;
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u32 saveDSPBSURF;
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u32 saveVCLK_DIVISOR_VGA0;
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u32 saveVCLK_DIVISOR_VGA1;
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u32 saveVCLK_POST_DIV;
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u32 saveVGACNTRL;
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u32 saveADPA;
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u32 saveLVDS;
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u32 saveDVOA;
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u32 saveDVOB;
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u32 saveDVOC;
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u32 savePP_ON;
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u32 savePP_OFF;
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u32 savePP_CONTROL;
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u32 savePP_CYCLE;
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u32 savePFIT_CONTROL;
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u32 savePaletteA[256];
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u32 savePaletteB[256];
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u32 saveSWF[17];
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u32 saveBLC_PWM_CTL;
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} drm_i915_private_t;
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enum intel_chip_family {
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CHIP_I8XX = 0x01,
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CHIP_I9XX = 0x02,
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CHIP_I915 = 0x04,
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CHIP_I965 = 0x08,
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};
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extern drm_ioctl_desc_t i915_ioctls[];
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extern int i915_max_ioctl;
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/* i915_dma.c */
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extern void i915_kernel_lost_context(drm_device_t * dev);
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extern int i915_driver_load(struct drm_device *, unsigned long flags);
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extern int i915_driver_unload(drm_device_t *dev);
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extern int i915_driver_firstopen(struct drm_device *dev);
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extern void i915_driver_lastclose(drm_device_t * dev);
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extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp);
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extern int i915_driver_device_is_agp(drm_device_t * dev);
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extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
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unsigned long arg);
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extern void i915_emit_breadcrumb(drm_device_t *dev);
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extern void i915_dispatch_flip(drm_device_t * dev, int pipes, int sync);
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extern int i915_emit_mi_flush(drm_device_t *dev, uint32_t flush);
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extern int i915_driver_firstopen(struct drm_device *dev);
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/* i915_irq.c */
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extern int i915_irq_emit(DRM_IOCTL_ARGS);
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extern int i915_irq_wait(DRM_IOCTL_ARGS);
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extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
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extern int i915_driver_vblank_wait2(drm_device_t *dev, unsigned int *sequence);
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extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
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extern void i915_driver_irq_preinstall(drm_device_t * dev);
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extern void i915_driver_irq_postinstall(drm_device_t * dev);
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extern void i915_driver_irq_uninstall(drm_device_t * dev);
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extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS);
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extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS);
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extern int i915_emit_irq(drm_device_t * dev);
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extern void i915_user_irq_on(drm_i915_private_t *dev_priv);
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extern void i915_user_irq_off(drm_i915_private_t *dev_priv);
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extern int i915_vblank_swap(DRM_IOCTL_ARGS);
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/* i915_mem.c */
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extern int i915_mem_alloc(DRM_IOCTL_ARGS);
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extern int i915_mem_free(DRM_IOCTL_ARGS);
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extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
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extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS);
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extern void i915_mem_takedown(struct mem_block **heap);
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extern void i915_mem_release(drm_device_t * dev,
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DRMFILE filp, struct mem_block *heap);
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#ifdef I915_HAVE_FENCE
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/* i915_fence.c */
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extern void i915_fence_handler(drm_device_t *dev);
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extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t class,
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uint32_t flags,
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uint32_t *sequence,
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uint32_t *native_type);
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extern void i915_poke_flush(drm_device_t *dev, uint32_t class);
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extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags);
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#endif
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#ifdef I915_HAVE_BUFFER
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/* i915_buffer.c */
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extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev);
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extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type);
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extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags);
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extern int i915_init_mem_type(drm_device_t *dev, uint32_t type,
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drm_mem_type_manager_t *man);
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extern uint32_t i915_evict_mask(drm_buffer_object_t *bo);
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extern int i915_move(drm_buffer_object_t *bo, int evict,
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int no_wait, drm_bo_mem_reg_t *new_mem);
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#endif
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/* modesetting */
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extern void intel_modeset_init(drm_device_t *dev);
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extern void intel_modeset_cleanup(drm_device_t *dev);
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#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
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#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
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#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
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#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
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#define I915_VERBOSE 0
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#define RING_LOCALS unsigned int outring, ringmask, outcount; \
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volatile char *virt;
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#define BEGIN_LP_RING(n) do { \
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if (I915_VERBOSE) \
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DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", \
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(n), __FUNCTION__); \
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if (dev_priv->ring.space < (n)*4) \
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i915_wait_ring(dev, (n)*4, __FUNCTION__); \
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outcount = 0; \
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outring = dev_priv->ring.tail; \
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ringmask = dev_priv->ring.tail_mask; \
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virt = dev_priv->ring.virtual_start; \
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} while (0)
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#define OUT_RING(n) do { \
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if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
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*(volatile unsigned int *)(virt + outring) = (n); \
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outcount++; \
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outring += 4; \
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outring &= ringmask; \
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} while (0)
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#define ADVANCE_LP_RING() do { \
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if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
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dev_priv->ring.tail = outring; \
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dev_priv->ring.space -= outcount * 4; \
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I915_WRITE(LP_RING + RING_TAIL, outring); \
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} while(0)
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extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
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/*
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* The Bridge device's PCI config space has information about the
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* fb aperture size and the amount of pre-reserved memory.
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*/
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#define INTEL_GMCH_CTRL 0x52
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#define INTEL_GMCH_ENABLED 0x4
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#define INTEL_GMCH_MEM_MASK 0x1
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#define INTEL_GMCH_MEM_64M 0x1
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#define INTEL_GMCH_MEM_128M 0
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#define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
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#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
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#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
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#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
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#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
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#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
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#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
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#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
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#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
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#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
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#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
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#define CMD_REPORT_HEAD (7<<23)
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#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
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#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
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#define CMD_MI_FLUSH (0x04 << 23)
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#define MI_NO_WRITE_FLUSH (1 << 2)
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#define MI_READ_FLUSH (1 << 0)
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#define MI_EXE_FLUSH (1 << 1)
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#define BB1_START_ADDR_MASK (~0x7)
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#define BB1_PROTECTED (1<<0)
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#define BB1_UNPROTECTED (0<<0)
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#define BB2_END_ADDR_MASK (~0x7)
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#define I915REG_HWSTAM 0x02098
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#define I915REG_INT_IDENTITY_R 0x020a4
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#define I915REG_INT_MASK_R 0x020a8
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#define I915REG_INT_ENABLE_R 0x020a0
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#define I915REG_INSTPM 0x020c0
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#define I915REG_PIPEASTAT 0x70024
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#define I915REG_PIPEBSTAT 0x71024
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#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
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#define I915_VBLANK_CLEAR (1UL<<1)
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#define GPIOA 0x5010
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#define GPIOB 0x5014
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#define GPIOC 0x5018
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#define GPIOD 0x501c
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#define GPIOE 0x5020
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#define GPIOF 0x5024
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#define GPIOG 0x5028
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#define GPIOH 0x502c
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# define GPIO_CLOCK_DIR_MASK (1 << 0)
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# define GPIO_CLOCK_DIR_IN (0 << 1)
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# define GPIO_CLOCK_DIR_OUT (1 << 1)
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# define GPIO_CLOCK_VAL_MASK (1 << 2)
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# define GPIO_CLOCK_VAL_OUT (1 << 3)
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# define GPIO_CLOCK_VAL_IN (1 << 4)
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# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
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# define GPIO_DATA_DIR_MASK (1 << 8)
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# define GPIO_DATA_DIR_IN (0 << 9)
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# define GPIO_DATA_DIR_OUT (1 << 9)
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# define GPIO_DATA_VAL_MASK (1 << 10)
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# define GPIO_DATA_VAL_OUT (1 << 11)
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# define GPIO_DATA_VAL_IN (1 << 12)
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# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
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#define SRX_INDEX 0x3c4
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#define SRX_DATA 0x3c5
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#define SR01 1
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#define SR01_SCREEN_OFF (1<<5)
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#define PPCR 0x61204
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#define PPCR_ON (1<<0)
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#define DVOA 0x61120
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#define DVOA_ON (1<<31)
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#define DVOB 0x61140
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#define DVOB_ON (1<<31)
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#define DVOC 0x61160
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#define DVOC_ON (1<<31)
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#define LVDS 0x61180
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#define LVDS_ON (1<<31)
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#define ADPA 0x61100
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#define ADPA_DPMS_MASK (~(3<<10))
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#define ADPA_DPMS_ON (0<<10)
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#define ADPA_DPMS_SUSPEND (1<<10)
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#define ADPA_DPMS_STANDBY (2<<10)
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#define ADPA_DPMS_OFF (3<<10)
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#define NOPID 0x2094
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#define LP_RING 0x2030
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#define HP_RING 0x2040
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#define RING_TAIL 0x00
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#define TAIL_ADDR 0x001FFFF8
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#define RING_HEAD 0x04
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#define HEAD_WRAP_COUNT 0xFFE00000
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#define HEAD_WRAP_ONE 0x00200000
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#define HEAD_ADDR 0x001FFFFC
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#define RING_START 0x08
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#define START_ADDR 0x0xFFFFF000
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#define RING_LEN 0x0C
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#define RING_NR_PAGES 0x001FF000
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#define RING_REPORT_MASK 0x00000006
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#define RING_REPORT_64K 0x00000002
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#define RING_REPORT_128K 0x00000004
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#define RING_NO_REPORT 0x00000000
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#define RING_VALID_MASK 0x00000001
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#define RING_VALID 0x00000001
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#define RING_INVALID 0x00000000
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#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
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#define SC_UPDATE_SCISSOR (0x1<<1)
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#define SC_ENABLE_MASK (0x1<<0)
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#define SC_ENABLE (0x1<<0)
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#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
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#define SCI_YMIN_MASK (0xffff<<16)
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#define SCI_XMIN_MASK (0xffff<<0)
|
|
#define SCI_YMAX_MASK (0xffff<<16)
|
|
#define SCI_XMAX_MASK (0xffff<<0)
|
|
|
|
#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
|
|
#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
|
|
#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
|
|
#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
|
|
#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
|
|
#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
|
|
#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
|
|
|
|
#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
|
|
|
|
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
|
|
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
|
|
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
|
|
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
|
|
|
|
#define MI_BATCH_BUFFER ((0x30<<23)|1)
|
|
#define MI_BATCH_BUFFER_START (0x31<<23)
|
|
#define MI_BATCH_BUFFER_END (0xA<<23)
|
|
#define MI_BATCH_NON_SECURE (1)
|
|
|
|
#define MI_WAIT_FOR_EVENT ((0x3<<23))
|
|
#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
|
|
#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
|
|
#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
|
|
|
|
#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
|
|
|
|
#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
|
|
#define ASYNC_FLIP (1<<22)
|
|
#define DISPLAY_PLANE_A (0<<20)
|
|
#define DISPLAY_PLANE_B (1<<20)
|
|
|
|
#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
|
|
|
|
#define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
|
|
#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
|
|
|
|
#define BLC_PWM_CTL 0x61254
|
|
#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
|
|
/**
|
|
* This is the most significant 15 bits of the number of backlight cycles in a
|
|
* complete cycle of the modulated backlight control.
|
|
*
|
|
* The actual value is this field multiplied by two.
|
|
*/
|
|
#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
|
|
#define BLM_LEGACY_MODE (1 << 16)
|
|
/**
|
|
* This is the number of cycles out of the backlight modulation cycle for which
|
|
* the backlight is on.
|
|
*
|
|
* This field must be no greater than the number of cycles in the complete
|
|
* backlight modulation cycle.
|
|
*/
|
|
#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
|
|
#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
|
|
|
|
#define I915_GCFGC 0xf0
|
|
#define I915_LOW_FREQUENCY_ENABLE (1 << 7)
|
|
#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
|
|
#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
|
|
#define I915_DISPLAY_CLOCK_MASK (7 << 4)
|
|
|
|
#define I855_HPLLCC 0xc0
|
|
#define I855_CLOCK_CONTROL_MASK (3 << 0)
|
|
#define I855_CLOCK_133_200 (0 << 0)
|
|
#define I855_CLOCK_100_200 (1 << 0)
|
|
#define I855_CLOCK_100_133 (2 << 0)
|
|
#define I855_CLOCK_166_250 (3 << 0)
|
|
|
|
/* I830 CRTC registers */
|
|
#define HTOTAL_A 0x60000
|
|
#define HBLANK_A 0x60004
|
|
#define HSYNC_A 0x60008
|
|
#define VTOTAL_A 0x6000c
|
|
#define VBLANK_A 0x60010
|
|
#define VSYNC_A 0x60014
|
|
#define PIPEASRC 0x6001c
|
|
#define BCLRPAT_A 0x60020
|
|
#define VSYNCSHIFT_A 0x60028
|
|
|
|
#define HTOTAL_B 0x61000
|
|
#define HBLANK_B 0x61004
|
|
#define HSYNC_B 0x61008
|
|
#define VTOTAL_B 0x6100c
|
|
#define VBLANK_B 0x61010
|
|
#define VSYNC_B 0x61014
|
|
#define PIPEBSRC 0x6101c
|
|
#define BCLRPAT_B 0x61020
|
|
#define VSYNCSHIFT_B 0x61028
|
|
|
|
#define PP_STATUS 0x61200
|
|
# define PP_ON (1 << 31)
|
|
/**
|
|
* Indicates that all dependencies of the panel are on:
|
|
*
|
|
* - PLL enabled
|
|
* - pipe enabled
|
|
* - LVDS/DVOB/DVOC on
|
|
*/
|
|
# define PP_READY (1 << 30)
|
|
# define PP_SEQUENCE_NONE (0 << 28)
|
|
# define PP_SEQUENCE_ON (1 << 28)
|
|
# define PP_SEQUENCE_OFF (2 << 28)
|
|
# define PP_SEQUENCE_MASK 0x30000000
|
|
#define PP_CONTROL 0x61204
|
|
# define POWER_TARGET_ON (1 << 0)
|
|
|
|
#define LVDSPP_ON 0x61208
|
|
#define LVDSPP_OFF 0x6120c
|
|
#define PP_CYCLE 0x61210
|
|
|
|
#define PFIT_CONTROL 0x61230
|
|
# define PFIT_ENABLE (1 << 31)
|
|
# define PFIT_PIPE_MASK (3 << 29)
|
|
# define PFIT_PIPE_SHIFT 29
|
|
# define VERT_INTERP_DISABLE (0 << 10)
|
|
# define VERT_INTERP_BILINEAR (1 << 10)
|
|
# define VERT_INTERP_MASK (3 << 10)
|
|
# define VERT_AUTO_SCALE (1 << 9)
|
|
# define HORIZ_INTERP_DISABLE (0 << 6)
|
|
# define HORIZ_INTERP_BILINEAR (1 << 6)
|
|
# define HORIZ_INTERP_MASK (3 << 6)
|
|
# define HORIZ_AUTO_SCALE (1 << 5)
|
|
# define PANEL_8TO6_DITHER_ENABLE (1 << 3)
|
|
|
|
#define PFIT_PGM_RATIOS 0x61234
|
|
# define PFIT_VERT_SCALE_MASK 0xfff00000
|
|
# define PFIT_HORIZ_SCALE_MASK 0x0000fff0
|
|
|
|
#define PFIT_AUTO_RATIOS 0x61238
|
|
|
|
|
|
#define DPLL_A 0x06014
|
|
#define DPLL_B 0x06018
|
|
# define DPLL_VCO_ENABLE (1 << 31)
|
|
# define DPLL_DVO_HIGH_SPEED (1 << 30)
|
|
# define DPLL_SYNCLOCK_ENABLE (1 << 29)
|
|
# define DPLL_VGA_MODE_DIS (1 << 28)
|
|
# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
|
|
# define DPLLB_MODE_LVDS (2 << 26) /* i915 */
|
|
# define DPLL_MODE_MASK (3 << 26)
|
|
# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
|
|
# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
|
|
# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
|
|
# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
|
|
# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
|
|
# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
|
|
/**
|
|
* The i830 generation, in DAC/serial mode, defines p1 as two plus this
|
|
* bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
|
|
*/
|
|
# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
|
|
/**
|
|
* The i830 generation, in LVDS mode, defines P1 as the bit number set within
|
|
* this field (only one bit may be set).
|
|
*/
|
|
# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
|
|
# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
|
|
# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
|
|
# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
|
|
# define PLL_REF_INPUT_DREFCLK (0 << 13)
|
|
# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
|
|
# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
|
|
# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
|
|
# define PLL_REF_INPUT_MASK (3 << 13)
|
|
# define PLL_LOAD_PULSE_PHASE_SHIFT 9
|
|
/*
|
|
* Parallel to Serial Load Pulse phase selection.
|
|
* Selects the phase for the 10X DPLL clock for the PCIe
|
|
* digital display port. The range is 4 to 13; 10 or more
|
|
* is just a flip delay. The default is 6
|
|
*/
|
|
# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
|
|
# define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
|
|
|
|
/**
|
|
* SDVO multiplier for 945G/GM. Not used on 965.
|
|
*
|
|
* \sa DPLL_MD_UDI_MULTIPLIER_MASK
|
|
*/
|
|
# define SDVO_MULTIPLIER_MASK 0x000000ff
|
|
# define SDVO_MULTIPLIER_SHIFT_HIRES 4
|
|
# define SDVO_MULTIPLIER_SHIFT_VGA 0
|
|
|
|
/** @defgroup DPLL_MD
|
|
* @{
|
|
*/
|
|
/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
|
|
#define DPLL_A_MD 0x0601c
|
|
/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
|
|
#define DPLL_B_MD 0x06020
|
|
/**
|
|
* UDI pixel divider, controlling how many pixels are stuffed into a packet.
|
|
*
|
|
* Value is pixels minus 1. Must be set to 1 pixel for SDVO.
|
|
*/
|
|
# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
|
|
# define DPLL_MD_UDI_DIVIDER_SHIFT 24
|
|
/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
|
|
# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
|
|
# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
|
|
/**
|
|
* SDVO/UDI pixel multiplier.
|
|
*
|
|
* SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
|
|
* clock rate is 10 times the DPLL clock. At low resolution/refresh rate
|
|
* modes, the bus rate would be below the limits, so SDVO allows for stuffing
|
|
* dummy bytes in the datastream at an increased clock rate, with both sides of
|
|
* the link knowing how many bytes are fill.
|
|
*
|
|
* So, for a mode with a dotclock of 65Mhz, we would want to double the clock
|
|
* rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
|
|
* set to 130Mhz, and the SDVO multiplier set to 2x in this register and
|
|
* through an SDVO command.
|
|
*
|
|
* This register field has values of multiplication factor minus 1, with
|
|
* a maximum multiplier of 5 for SDVO.
|
|
*/
|
|
# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
|
|
# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
|
|
/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
|
|
* This best be set to the default value (3) or the CRT won't work. No,
|
|
* I don't entirely understand what this does...
|
|
*/
|
|
# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
|
|
# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
|
|
/** @} */
|
|
|
|
#define DPLL_TEST 0x606c
|
|
# define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
|
|
# define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
|
|
# define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
|
|
# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
|
|
# define DPLLB_TEST_N_BYPASS (1 << 19)
|
|
# define DPLLB_TEST_M_BYPASS (1 << 18)
|
|
# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
|
|
# define DPLLA_TEST_N_BYPASS (1 << 3)
|
|
# define DPLLA_TEST_M_BYPASS (1 << 2)
|
|
# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
|
|
|
|
#define ADPA 0x61100
|
|
#define ADPA_DAC_ENABLE (1<<31)
|
|
#define ADPA_DAC_DISABLE 0
|
|
#define ADPA_PIPE_SELECT_MASK (1<<30)
|
|
#define ADPA_PIPE_A_SELECT 0
|
|
#define ADPA_PIPE_B_SELECT (1<<30)
|
|
#define ADPA_USE_VGA_HVPOLARITY (1<<15)
|
|
#define ADPA_SETS_HVPOLARITY 0
|
|
#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
|
|
#define ADPA_VSYNC_CNTL_ENABLE 0
|
|
#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
|
|
#define ADPA_HSYNC_CNTL_ENABLE 0
|
|
#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
|
|
#define ADPA_VSYNC_ACTIVE_LOW 0
|
|
#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
|
|
#define ADPA_HSYNC_ACTIVE_LOW 0
|
|
|
|
#define FPA0 0x06040
|
|
#define FPA1 0x06044
|
|
#define FPB0 0x06048
|
|
#define FPB1 0x0604c
|
|
# define FP_N_DIV_MASK 0x003f0000
|
|
# define FP_N_DIV_SHIFT 16
|
|
# define FP_M1_DIV_MASK 0x00003f00
|
|
# define FP_M1_DIV_SHIFT 8
|
|
# define FP_M2_DIV_MASK 0x0000003f
|
|
# define FP_M2_DIV_SHIFT 0
|
|
|
|
|
|
#define PORT_HOTPLUG_EN 0x61110
|
|
# define SDVOB_HOTPLUG_INT_EN (1 << 26)
|
|
# define SDVOC_HOTPLUG_INT_EN (1 << 25)
|
|
# define TV_HOTPLUG_INT_EN (1 << 18)
|
|
# define CRT_HOTPLUG_INT_EN (1 << 9)
|
|
# define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
|
|
|
|
#define PORT_HOTPLUG_STAT 0x61114
|
|
# define CRT_HOTPLUG_INT_STATUS (1 << 11)
|
|
# define TV_HOTPLUG_INT_STATUS (1 << 10)
|
|
# define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
|
|
# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
|
|
# define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
|
|
# define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
|
|
# define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
|
|
# define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
|
|
|
|
#define SDVOB 0x61140
|
|
#define SDVOC 0x61160
|
|
#define SDVO_ENABLE (1 << 31)
|
|
#define SDVO_PIPE_B_SELECT (1 << 30)
|
|
#define SDVO_STALL_SELECT (1 << 29)
|
|
#define SDVO_INTERRUPT_ENABLE (1 << 26)
|
|
/**
|
|
* 915G/GM SDVO pixel multiplier.
|
|
*
|
|
* Programmed value is multiplier - 1, up to 5x.
|
|
*
|
|
* \sa DPLL_MD_UDI_MULTIPLIER_MASK
|
|
*/
|
|
#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
|
|
#define SDVO_PORT_MULTIPLY_SHIFT 23
|
|
#define SDVO_PHASE_SELECT_MASK (15 << 19)
|
|
#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
|
|
#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
|
|
#define SDVOC_GANG_MODE (1 << 16)
|
|
#define SDVO_BORDER_ENABLE (1 << 7)
|
|
#define SDVOB_PCIE_CONCURRENCY (1 << 3)
|
|
#define SDVO_DETECTED (1 << 2)
|
|
/* Bits to be preserved when writing */
|
|
#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
|
|
#define SDVOC_PRESERVE_MASK (1 << 17)
|
|
|
|
/** @defgroup LVDS
|
|
* @{
|
|
*/
|
|
/**
|
|
* This register controls the LVDS output enable, pipe selection, and data
|
|
* format selection.
|
|
*
|
|
* All of the clock/data pairs are force powered down by power sequencing.
|
|
*/
|
|
#define LVDS 0x61180
|
|
/**
|
|
* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
|
|
* the DPLL semantics change when the LVDS is assigned to that pipe.
|
|
*/
|
|
# define LVDS_PORT_EN (1 << 31)
|
|
/** Selects pipe B for LVDS data. Must be set on pre-965. */
|
|
# define LVDS_PIPEB_SELECT (1 << 30)
|
|
|
|
/**
|
|
* Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
|
|
* pixel.
|
|
*/
|
|
# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
|
|
# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
|
|
# define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
|
|
/**
|
|
* Controls the A3 data pair, which contains the additional LSBs for 24 bit
|
|
* mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
|
|
* on.
|
|
*/
|
|
# define LVDS_A3_POWER_MASK (3 << 6)
|
|
# define LVDS_A3_POWER_DOWN (0 << 6)
|
|
# define LVDS_A3_POWER_UP (3 << 6)
|
|
/**
|
|
* Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
|
|
* is set.
|
|
*/
|
|
# define LVDS_CLKB_POWER_MASK (3 << 4)
|
|
# define LVDS_CLKB_POWER_DOWN (0 << 4)
|
|
# define LVDS_CLKB_POWER_UP (3 << 4)
|
|
|
|
/**
|
|
* Controls the B0-B3 data pairs. This must be set to match the DPLL p2
|
|
* setting for whether we are in dual-channel mode. The B3 pair will
|
|
* additionally only be powered up when LVDS_A3_POWER_UP is set.
|
|
*/
|
|
# define LVDS_B0B3_POWER_MASK (3 << 2)
|
|
# define LVDS_B0B3_POWER_DOWN (0 << 2)
|
|
# define LVDS_B0B3_POWER_UP (3 << 2)
|
|
|
|
#define PIPEACONF 0x70008
|
|
#define PIPEACONF_ENABLE (1<<31)
|
|
#define PIPEACONF_DISABLE 0
|
|
#define PIPEACONF_DOUBLE_WIDE (1<<30)
|
|
#define I965_PIPECONF_ACTIVE (1<<30)
|
|
#define PIPEACONF_SINGLE_WIDE 0
|
|
#define PIPEACONF_PIPE_UNLOCKED 0
|
|
#define PIPEACONF_PIPE_LOCKED (1<<25)
|
|
#define PIPEACONF_PALETTE 0
|
|
#define PIPEACONF_GAMMA (1<<24)
|
|
#define PIPECONF_FORCE_BORDER (1<<25)
|
|
#define PIPECONF_PROGRESSIVE (0 << 21)
|
|
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
|
|
#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
|
|
|
|
#define PIPEBCONF 0x71008
|
|
#define PIPEBCONF_ENABLE (1<<31)
|
|
#define PIPEBCONF_DISABLE 0
|
|
#define PIPEBCONF_DOUBLE_WIDE (1<<30)
|
|
#define PIPEBCONF_DISABLE 0
|
|
#define PIPEBCONF_GAMMA (1<<24)
|
|
#define PIPEBCONF_PALETTE 0
|
|
|
|
#define PIPEBGCMAXRED 0x71010
|
|
#define PIPEBGCMAXGREEN 0x71014
|
|
#define PIPEBGCMAXBLUE 0x71018
|
|
#define PIPEBSTAT 0x71024
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#define PIPEBFRAMEHIGH 0x71040
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#define PIPEBFRAMEPIXEL 0x71044
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#define DSPACNTR 0x70180
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#define DSPBCNTR 0x71180
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#define DISPLAY_PLANE_ENABLE (1<<31)
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#define DISPLAY_PLANE_DISABLE 0
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#define DISPPLANE_GAMMA_ENABLE (1<<30)
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#define DISPPLANE_GAMMA_DISABLE 0
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#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
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#define DISPPLANE_8BPP (0x2<<26)
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#define DISPPLANE_15_16BPP (0x4<<26)
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#define DISPPLANE_16BPP (0x5<<26)
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#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
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#define DISPPLANE_32BPP (0x7<<26)
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#define DISPPLANE_STEREO_ENABLE (1<<25)
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#define DISPPLANE_STEREO_DISABLE 0
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#define DISPPLANE_SEL_PIPE_MASK (1<<24)
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#define DISPPLANE_SEL_PIPE_A 0
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#define DISPPLANE_SEL_PIPE_B (1<<24)
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#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
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#define DISPPLANE_SRC_KEY_DISABLE 0
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#define DISPPLANE_LINE_DOUBLE (1<<20)
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#define DISPPLANE_NO_LINE_DOUBLE 0
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#define DISPPLANE_STEREO_POLARITY_FIRST 0
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#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
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/* plane B only */
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#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
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#define DISPPLANE_ALPHA_TRANS_DISABLE 0
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#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
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#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
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#define DSPABASE 0x70184
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#define DSPASTRIDE 0x70188
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#define DSPBBASE 0x71184
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#define DSPBADDR DSPBBASE
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#define DSPBSTRIDE 0x71188
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#define DSPAKEYVAL 0x70194
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#define DSPAKEYMASK 0x70198
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#define DSPAPOS 0x7018C /* reserved */
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#define DSPASIZE 0x70190
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#define DSPBPOS 0x7118C
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#define DSPBSIZE 0x71190
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#define DSPASURF 0x7019C
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#define DSPATILEOFF 0x701A4
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#define DSPBSURF 0x7119C
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#define DSPBTILEOFF 0x711A4
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#define VGACNTRL 0x71400
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# define VGA_DISP_DISABLE (1 << 31)
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# define VGA_2X_MODE (1 << 30)
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# define VGA_PIPE_B_SELECT (1 << 29)
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/*
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* Palette registers
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*/
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#define PALETTE_A 0x0a000
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#define PALETTE_B 0x0a800
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#define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC)
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#define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG)
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#define IS_I85X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG)
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#define IS_I855(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG)
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#define IS_I865G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82865_IG)
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#define IS_I915G(pI810) (dev->pci_device == PCI_DEVICE_ID_INTEL_82915G_IG)/* || dev->pci_device == PCI_DEVICE_ID_INTELPCI_CHIP_E7221_G)*/
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#define IS_I915GM(pI810) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82915GM_IG)
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#define IS_I945G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945G_IG)
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#define IS_I945GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GM_IG)
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#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
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(dev)->pci_device == 0x2982 || \
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(dev)->pci_device == 0x2992 || \
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(dev)->pci_device == 0x29A2)
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#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810))
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#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810))
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#endif
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