683 lines
17 KiB
C
683 lines
17 KiB
C
/*
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* Copyright 2004 The Unichrome Project. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE UNICHROME PROJECT, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Author: Thomas Hellström 2004.
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* This code was written using docs obtained under NDA from VIA Inc.
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*
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* Don't run this code directly on an AGP buffer. Due to cache problems it will
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* be very slow.
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*/
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#include "via_3d_reg.h"
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#include "via.h"
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#include "drmP.h"
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typedef enum{
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state_command,
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state_header2,
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state_header1,
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state_error
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} verifier_state_t;
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typedef enum{
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no_sequence = 0,
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z_address,
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dest_address,
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tex_address
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}sequence_t;
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typedef enum{
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no_check = 0,
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check_for_header2,
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check_for_header1,
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check_for_header2_err,
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check_for_header1_err,
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check_for_fire,
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check_z_buffer_addr0,
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check_z_buffer_addr1,
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check_z_buffer_addr_mode,
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check_destination_addr0,
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check_destination_addr1,
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check_destination_addr_mode,
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check_for_dummy,
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check_for_dd,
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check_texture_addr0,
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check_texture_addr1,
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check_texture_addr2,
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check_texture_addr3,
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check_texture_addr4,
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check_texture_addr5,
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check_texture_addr6,
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check_texture_addr7,
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check_texture_addr8,
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check_texture_addr_mode,
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forbidden_command
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}hazard_t;
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/*
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* Associates each hazard above with a possible multi-command
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* sequence. For example an address that is split over multiple
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* commands and that needs to be checked at the first command
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* that does not include any part of the address.
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*/
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static sequence_t seqs[] = {
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no_sequence,
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no_sequence,
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no_sequence,
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no_sequence,
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no_sequence,
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no_sequence,
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z_address,
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z_address,
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z_address,
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dest_address,
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dest_address,
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dest_address,
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no_sequence,
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no_sequence,
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tex_address,
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tex_address,
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tex_address,
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tex_address,
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tex_address,
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tex_address,
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tex_address,
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tex_address,
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tex_address,
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tex_address,
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no_sequence
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};
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typedef struct{
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unsigned int code;
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hazard_t hz;
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} hz_init_t;
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static hz_init_t init_table1[] = {
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{0xf2, check_for_header2_err},
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{0xf0, check_for_header1_err},
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{0xee, check_for_fire},
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{0xcc, check_for_dummy},
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{0xdd, check_for_dd},
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{0x00, no_check},
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{0x10, check_z_buffer_addr0},
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{0x11, check_z_buffer_addr1},
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{0x12, check_z_buffer_addr_mode},
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{0x13, no_check},
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{0x14, no_check},
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{0x15, no_check},
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{0x23, no_check},
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{0x24, no_check},
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{0x33, no_check},
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{0x34, no_check},
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{0x35, no_check},
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{0x36, no_check},
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{0x37, no_check},
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{0x38, no_check},
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{0x39, no_check},
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{0x3A, no_check},
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{0x3B, no_check},
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{0x3C, no_check},
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{0x3D, no_check},
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{0x3E, no_check},
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{0x40, check_destination_addr0},
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{0x41, check_destination_addr1},
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{0x42, check_destination_addr_mode},
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{0x43, no_check},
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{0x44, no_check},
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{0x50, no_check},
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{0x51, no_check},
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{0x52, no_check},
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{0x53, no_check},
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{0x54, no_check},
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{0x55, no_check},
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{0x56, no_check},
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{0x57, no_check},
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{0x58, no_check},
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{0x70, no_check},
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{0x71, no_check},
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{0x78, no_check},
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{0x79, no_check},
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{0x7A, no_check},
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{0x7B, no_check},
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{0x7C, no_check},
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{0x7D, no_check}
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};
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static hz_init_t init_table2[] = {
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{0xf2, check_for_header2_err},
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{0xf0, check_for_header1_err},
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{0xee, check_for_fire},
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{0xcc, check_for_dummy},
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{0x00, check_texture_addr0},
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{0x01, check_texture_addr0},
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{0x02, check_texture_addr0},
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{0x03, check_texture_addr0},
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{0x04, check_texture_addr0},
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{0x05, check_texture_addr0},
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{0x06, check_texture_addr0},
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{0x07, check_texture_addr0},
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{0x08, check_texture_addr0},
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{0x09, check_texture_addr0},
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{0x20, check_texture_addr1},
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{0x21, check_texture_addr1},
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{0x22, check_texture_addr1},
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{0x23, check_texture_addr4},
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{0x2B, check_texture_addr3},
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{0x2C, check_texture_addr3},
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{0x2D, check_texture_addr3},
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{0x2E, check_texture_addr3},
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{0x2F, check_texture_addr3},
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{0x30, check_texture_addr3},
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{0x31, check_texture_addr3},
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{0x32, check_texture_addr3},
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{0x33, check_texture_addr3},
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{0x34, check_texture_addr3},
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{0x4B, check_texture_addr5},
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{0x4C, check_texture_addr6},
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{0x51, check_texture_addr7},
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{0x52, check_texture_addr8},
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{0x77, check_texture_addr2},
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{0x78, no_check},
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{0x79, no_check},
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{0x7A, no_check},
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{0x7B, check_texture_addr_mode},
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{0x7C, no_check},
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{0x7D, no_check},
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{0x7E, no_check},
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{0x7F, no_check},
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{0x80, no_check},
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{0x81, no_check},
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{0x82, no_check},
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{0x83, no_check},
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{0x85, no_check},
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{0x86, no_check},
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{0x87, no_check},
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{0x88, no_check},
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{0x89, no_check},
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{0x8A, no_check},
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{0x90, no_check},
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{0x91, no_check},
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{0x92, no_check},
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{0x93, no_check}
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};
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static hz_init_t init_table3[] = {
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{0xf2, check_for_header2_err},
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{0xf0, check_for_header1_err},
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{0xcc, check_for_dummy},
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{0x00, no_check}
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};
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static hazard_t table1[256];
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static hazard_t table2[256];
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static hazard_t table3[256];
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typedef struct{
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unsigned texture;
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uint32_t z_addr;
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uint32_t d_addr;
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uint32_t t_addr[2][10];
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uint32_t pitch[2][10];
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uint32_t height[2][10];
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uint32_t tex_level_lo[2];
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uint32_t tex_level_hi[2];
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sequence_t unfinished;
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int agp_texture;
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drm_device_t *dev;
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drm_map_t *map_cache;
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} sequence_context_t;
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static sequence_context_t hc_sequence;
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/*
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* Partially stolen from drm_memory.h
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*/
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static __inline__ drm_map_t *
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via_drm_lookup_agp_map (sequence_context_t *seq, unsigned long offset, unsigned long size,
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drm_device_t *dev)
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{
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struct list_head *list;
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drm_map_list_t *r_list;
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drm_map_t *map = seq->map_cache;
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if (map && map->offset <= offset && (offset + size) <= (map->offset + map->size)) {
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return map;
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}
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list_for_each(list, &dev->maplist->head) {
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r_list = (drm_map_list_t *) list;
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map = r_list->map;
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if (!map)
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continue;
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if (map->offset <= offset && (offset + size) <= (map->offset + map->size) &&
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!(map->flags & _DRM_RESTRICTED) && (map->type == _DRM_AGP)) {
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seq->map_cache = map;
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return map;
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}
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}
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return NULL;
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}
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/*
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* Require that all AGP texture levels reside in the same AGP map which should
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* be mappable by the client. This is not a big restriction.
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* FIXME: To actually enforce this security policy strictly, drm_rmmap
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* would have to wait for dma quiescent before removing an AGP map.
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* The via_drm_lookup_agp_map call in reality seems to take
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* very little CPU time.
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*/
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static __inline__ int
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finish_current_sequence(sequence_context_t *cur_seq)
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{
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switch(cur_seq->unfinished) {
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case z_address:
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DRM_DEBUG("Z Buffer start address is 0x%x\n", cur_seq->z_addr);
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break;
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case dest_address:
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DRM_DEBUG("Destination start address is 0x%x\n", cur_seq->d_addr);
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break;
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case tex_address:
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if (cur_seq->agp_texture) {
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unsigned start = cur_seq->tex_level_lo[cur_seq->texture];
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unsigned end = cur_seq->tex_level_hi[cur_seq->texture];
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unsigned long lo=~0, hi=0, tmp;
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uint32_t *addr, *pitch, *height, tex;
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unsigned i;
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if (end > 9) end = 9;
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if (start > 9) start = 9;
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addr =&(cur_seq->t_addr[tex = cur_seq->texture][start]);
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pitch = &(cur_seq->pitch[tex][start]);
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height = &(cur_seq->height[tex][start]);
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for (i=start; i<= end; ++i) {
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tmp = *addr++;
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if (tmp < lo) lo = tmp;
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tmp += (*height++ << *pitch++);
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if (tmp > hi) hi = tmp;
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}
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if (! via_drm_lookup_agp_map (cur_seq, lo, hi - lo, cur_seq->dev)) {
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DRM_ERROR("AGP texture is not in allowed map\n");
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return 2;
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}
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}
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break;
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default:
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break;
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}
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cur_seq->unfinished = no_sequence;
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return 0;
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}
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static __inline__ int
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investigate_hazard( uint32_t cmd, hazard_t hz, sequence_context_t *cur_seq)
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{
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register uint32_t tmp, *tmp_addr;
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if (cur_seq->unfinished && (cur_seq->unfinished != seqs[hz])) {
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int ret;
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if ((ret = finish_current_sequence(cur_seq))) return ret;
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}
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switch(hz) {
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case check_for_header2:
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if (cmd == HALCYON_HEADER2) return 1;
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return 0;
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case check_for_header1:
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if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) return 1;
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return 0;
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case check_for_header2_err:
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if (cmd == HALCYON_HEADER2) return 1;
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DRM_ERROR("Illegal DMA HALCYON_HEADER2 command\n");
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break;
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case check_for_header1_err:
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if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1) return 1;
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DRM_ERROR("Illegal DMA HALCYON_HEADER1 command\n");
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break;
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case check_for_fire:
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if ((cmd & HALCYON_FIREMASK) == HALCYON_FIRECMD) return 1;
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DRM_ERROR("Illegal DMA HALCYON_FIRECMD command\n");
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break;
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case check_for_dummy:
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if (HC_DUMMY == cmd) return 0;
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DRM_ERROR("Illegal DMA HC_DUMMY command\n");
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break;
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case check_for_dd:
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if (0xdddddddd == cmd) return 0;
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DRM_ERROR("Illegal DMA 0xdddddddd command\n");
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break;
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case check_z_buffer_addr0:
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cur_seq->unfinished = z_address;
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cur_seq->z_addr = (cur_seq->z_addr & 0xFF000000) |
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(cmd & 0x00FFFFFF);
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return 0;
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case check_z_buffer_addr1:
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cur_seq->unfinished = z_address;
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cur_seq->z_addr = (cur_seq->z_addr & 0x00FFFFFF) |
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((cmd & 0xFF) << 24);
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return 0;
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case check_z_buffer_addr_mode:
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cur_seq->unfinished = z_address;
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if ((cmd & 0x0000C000) == 0) return 0;
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DRM_ERROR("Attempt to place Z buffer in system memory\n");
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return 2;
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case check_destination_addr0:
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cur_seq->unfinished = dest_address;
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cur_seq->d_addr = (cur_seq->d_addr & 0xFF000000) |
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(cmd & 0x00FFFFFF);
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return 0;
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case check_destination_addr1:
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cur_seq->unfinished = dest_address;
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cur_seq->d_addr = (cur_seq->d_addr & 0x00FFFFFF) |
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((cmd & 0xFF) << 24);
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return 0;
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case check_destination_addr_mode:
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cur_seq->unfinished = dest_address;
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if ((cmd & 0x0000C000) == 0) return 0;
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DRM_ERROR("Attempt to place 3D drawing buffer in system memory\n");
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return 2;
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case check_texture_addr0:
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cur_seq->unfinished = tex_address;
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tmp = (cmd >> 24);
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tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp];
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*tmp_addr = (*tmp_addr & 0xFF000000) | (cmd & 0x00FFFFFF);
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return 0;
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case check_texture_addr1:
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cur_seq->unfinished = tex_address;
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tmp = ((cmd >> 24) - 0x20);
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tmp += tmp << 1;
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tmp_addr = &cur_seq->t_addr[cur_seq->texture][tmp];
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*tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24);
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tmp_addr++;
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*tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF00) << 16);
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tmp_addr++;
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*tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF0000) << 8);
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return 0;
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case check_texture_addr2:
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cur_seq->unfinished = tex_address;
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cur_seq->tex_level_lo[tmp = cur_seq->texture] = cmd & 0x3F;
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cur_seq->tex_level_hi[tmp] = (cmd & 0xFC0) >> 6;
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return 0;
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case check_texture_addr3:
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cur_seq->unfinished = tex_address;
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tmp = ((cmd >> 24) - 0x2B);
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cur_seq->pitch[cur_seq->texture][tmp] = (cmd & 0x00F00000) >> 20;
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if (!tmp && (cmd & 0x000FFFFF)) {
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DRM_ERROR("Unimplemented texture level 0 pitch mode.\n");
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return 2;
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}
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return 0;
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case check_texture_addr4:
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cur_seq->unfinished = tex_address;
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tmp_addr = &cur_seq->t_addr[cur_seq->texture][9];
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*tmp_addr = (*tmp_addr & 0x00FFFFFF) | ((cmd & 0xFF) << 24);
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return 0;
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case check_texture_addr5:
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case check_texture_addr6:
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cur_seq->unfinished = tex_address;
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/*
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* Texture width. We don't care since we have the pitch.
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*/
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return 0;
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case check_texture_addr7:
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cur_seq->unfinished = tex_address;
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tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
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tmp_addr[5] = 1 << ((cmd & 0x00F00000) >> 20);
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tmp_addr[4] = 1 << ((cmd & 0x000F0000) >> 16);
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tmp_addr[3] = 1 << ((cmd & 0x0000F000) >> 12);
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tmp_addr[2] = 1 << ((cmd & 0x00000F00) >> 8);
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tmp_addr[1] = 1 << ((cmd & 0x000000F0) >> 4);
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tmp_addr[0] = 1 << (cmd & 0x0000000F);
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return 0;
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case check_texture_addr8:
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cur_seq->unfinished = tex_address;
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tmp_addr = &(cur_seq->height[cur_seq->texture][0]);
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tmp_addr[9] = 1 << ((cmd & 0x0000F000) >> 12);
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tmp_addr[8] = 1 << ((cmd & 0x00000F00) >> 8);
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tmp_addr[7] = 1 << ((cmd & 0x000000F0) >> 4);
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tmp_addr[6] = 1 << (cmd & 0x0000000F);
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return 0;
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case check_texture_addr_mode:
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cur_seq->unfinished = tex_address;
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if ( 2 != (tmp = cmd & 0x00000003)) {
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cur_seq->agp_texture = (tmp == 3);
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return 0;
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}
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DRM_ERROR("Attempt to fetch texture from system memory.\n");
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return 2;
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|
default:
|
|
DRM_ERROR("Illegal DMA data: 0x%x\n", cmd);
|
|
return 2;
|
|
}
|
|
return 2;
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ verifier_state_t
|
|
via_check_header2( uint32_t const **buffer, const uint32_t *buf_end )
|
|
{
|
|
uint32_t cmd;
|
|
int hz_mode;
|
|
hazard_t hz;
|
|
const uint32_t *buf = *buffer;
|
|
const hazard_t *hz_table;
|
|
|
|
if ((buf_end - buf) < 2) {
|
|
DRM_ERROR("Illegal termination of DMA HALCYON_HEADER2 sequence.\n");
|
|
return state_error;
|
|
}
|
|
buf++;
|
|
cmd = (*buf++ & 0xFFFF0000) >> 16;
|
|
|
|
switch(cmd) {
|
|
case HC_ParaType_CmdVdata:
|
|
|
|
/*
|
|
* Command vertex data.
|
|
* It is assumed that the command regulator remains in this state
|
|
* until it encounters a double fire command or a header2 data.
|
|
* CHECK: Could vertex data accidently be header2 or fire?
|
|
* CHECK: What does the regulator do if it encounters a header1
|
|
* cmd?
|
|
*/
|
|
|
|
while (buf < buf_end) {
|
|
if (*buf == HALCYON_HEADER2) break;
|
|
if ((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD) {
|
|
buf++;
|
|
if ((buf < buf_end) &&
|
|
((*buf & HALCYON_FIREMASK) == HALCYON_FIRECMD))
|
|
buf++;
|
|
if ((buf < buf_end) &&
|
|
((*buf & HALCYON_CMDBMASK) != HC_ACMD_HCmdB))
|
|
break;
|
|
}
|
|
buf++;
|
|
}
|
|
*buffer = buf;
|
|
return state_command;
|
|
|
|
case HC_ParaType_NotTex:
|
|
hz_table = table1;
|
|
break;
|
|
case HC_ParaType_Tex:
|
|
hc_sequence.texture = 0;
|
|
hz_table = table2;
|
|
break;
|
|
case (HC_ParaType_Tex | (HC_SubType_Tex1 << 8)):
|
|
hc_sequence.texture = 1;
|
|
hz_table = table2;
|
|
break;
|
|
case (HC_ParaType_Tex | (HC_SubType_TexGeneral << 8)):
|
|
hz_table = table3;
|
|
break;
|
|
default:
|
|
|
|
/*
|
|
* There are some unimplemented HC_ParaTypes here, that
|
|
* need to be implemented if the Mesa driver is extended.
|
|
*/
|
|
|
|
DRM_ERROR("Invalid or unimplemented HALCYON_HEADER2 "
|
|
"DMA subcommand: 0x%x\n", cmd);
|
|
*buffer = buf;
|
|
return state_error;
|
|
}
|
|
|
|
while(buf < buf_end) {
|
|
cmd = *buf++;
|
|
if ((hz = hz_table[cmd >> 24])) {
|
|
if ((hz_mode = investigate_hazard(cmd, hz, &hc_sequence))) {
|
|
if (hz_mode == 1) {
|
|
buf--;
|
|
break;
|
|
}
|
|
return state_error;
|
|
}
|
|
} else if (hc_sequence.unfinished &&
|
|
finish_current_sequence(&hc_sequence)) {
|
|
return state_error;
|
|
}
|
|
}
|
|
if (hc_sequence.unfinished && finish_current_sequence(&hc_sequence)) {
|
|
return state_error;
|
|
}
|
|
*buffer = buf;
|
|
return state_command;
|
|
}
|
|
|
|
|
|
static __inline__ verifier_state_t
|
|
via_check_header1( uint32_t const **buffer, const uint32_t *buf_end )
|
|
{
|
|
uint32_t cmd;
|
|
const uint32_t *buf = *buffer;
|
|
verifier_state_t ret = state_command;
|
|
|
|
while (buf < buf_end) {
|
|
cmd = *buf;
|
|
if ((cmd > ((0x3FF >> 2) | HALCYON_HEADER1)) &&
|
|
(cmd < ((0xC00 >> 2) | HALCYON_HEADER1))) {
|
|
if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
|
|
break;
|
|
DRM_ERROR("Invalid HALCYON_HEADER1 command. "
|
|
"Attempt to access 3D- or command burst area.\n");
|
|
ret = state_error;
|
|
break;
|
|
} else if (cmd > ((0xCFF >> 2) | HALCYON_HEADER1)) {
|
|
if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1)
|
|
break;
|
|
DRM_ERROR("Invalid HALCYON_HEADER1 command. "
|
|
"Attempt to access VGA registers.\n");
|
|
ret = state_error;
|
|
break;
|
|
} else {
|
|
buf += 2;
|
|
}
|
|
}
|
|
*buffer = buf;
|
|
return ret;
|
|
}
|
|
|
|
|
|
|
|
int
|
|
via_verify_command_stream(const uint32_t * buf, unsigned int size, drm_device_t *dev)
|
|
{
|
|
|
|
uint32_t cmd;
|
|
const uint32_t *buf_end = buf + ( size >> 2 );
|
|
verifier_state_t state = state_command;
|
|
|
|
hc_sequence.dev = dev;
|
|
hc_sequence.unfinished = no_sequence;
|
|
hc_sequence.map_cache = NULL;
|
|
|
|
while (buf < buf_end) {
|
|
switch (state) {
|
|
case state_header2:
|
|
state = via_check_header2( &buf, buf_end );
|
|
break;
|
|
case state_header1:
|
|
state = via_check_header1( &buf, buf_end );
|
|
break;
|
|
case state_command:
|
|
if (HALCYON_HEADER2 == (cmd = *buf))
|
|
state = state_header2;
|
|
else if ((cmd & HALCYON_HEADER1MASK) == HALCYON_HEADER1)
|
|
state = state_header1;
|
|
else {
|
|
DRM_ERROR("Invalid / Unimplemented DMA HEADER command. 0x%x\n",
|
|
cmd);
|
|
state = state_error;
|
|
}
|
|
break;
|
|
case state_error:
|
|
default:
|
|
return DRM_ERR(EINVAL);
|
|
}
|
|
}
|
|
return (state == state_error) ? DRM_ERR(EINVAL) : 0;
|
|
}
|
|
|
|
static void
|
|
setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size)
|
|
{
|
|
int i;
|
|
|
|
for(i=0; i<256; ++i) {
|
|
table[i] = forbidden_command;
|
|
}
|
|
|
|
for(i=0; i<size; ++i) {
|
|
table[init_table[i].code] = init_table[i].hz;
|
|
}
|
|
}
|
|
|
|
void
|
|
via_init_command_verifier( void )
|
|
{
|
|
hc_sequence.texture = 0;
|
|
setup_hazard_table(init_table1, table1, sizeof(init_table1) / sizeof(hz_init_t));
|
|
setup_hazard_table(init_table2, table2, sizeof(init_table2) / sizeof(hz_init_t));
|
|
setup_hazard_table(init_table3, table3, sizeof(init_table3) / sizeof(hz_init_t));
|
|
}
|