218 lines
5.8 KiB
C
218 lines
5.8 KiB
C
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/****************************************************************************
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* Copyright (C) 2003-2006 by XGI Technology, Taiwan.
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* *
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* All Rights Reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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* *
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL XGI AND/OR
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* ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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***************************************************************************/
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#ifndef _XGI_REGS_H_
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#define _XGI_REGS_H_
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#include "drmP.h"
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#include "drm.h"
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/* Hardware access functions */
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static inline void OUT3C5B(struct drm_map * map, u8 index, u8 data)
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{
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DRM_WRITE8(map, 0x3C4, index);
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DRM_WRITE8(map, 0x3C5, data);
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}
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static inline void OUT3X5B(struct drm_map * map, u8 index, u8 data)
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{
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DRM_WRITE8(map, 0x3D4, index);
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DRM_WRITE8(map, 0x3D5, data);
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}
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static inline void OUT3CFB(struct drm_map * map, u8 index, u8 data)
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{
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DRM_WRITE8(map, 0x3CE, index);
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DRM_WRITE8(map, 0x3CF, data);
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}
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static inline u8 IN3C5B(struct drm_map * map, u8 index)
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{
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DRM_WRITE8(map, 0x3C4, index);
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return DRM_READ8(map, 0x3C5);
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}
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static inline u8 IN3X5B(struct drm_map * map, u8 index)
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{
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DRM_WRITE8(map, 0x3D4, index);
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return DRM_READ8(map, 0x3D5);
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}
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static inline u8 IN3CFB(struct drm_map * map, u8 index)
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{
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DRM_WRITE8(map, 0x3CE, index);
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return DRM_READ8(map, 0x3CF);
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}
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/*
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* Graphic engine register (2d/3d) acessing interface
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*/
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static inline void dwWriteReg(struct drm_map * map, u32 addr, u32 data)
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{
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DRM_INFO("mmio_map->handle = 0x%p, addr = 0x%x, data = 0x%x\n",
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map->handle, addr, data);
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DRM_WRITE32(map, addr, data);
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}
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static inline void xgi_enable_mmio(struct xgi_info * info)
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{
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u8 protect = 0;
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u8 temp;
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/* Unprotect registers */
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DRM_WRITE8(info->mmio_map, 0x3C4, 0x11);
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protect = DRM_READ8(info->mmio_map, 0x3C5);
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DRM_WRITE8(info->mmio_map, 0x3C5, 0x92);
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DRM_WRITE8(info->mmio_map, 0x3D4, 0x3A);
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temp = DRM_READ8(info->mmio_map, 0x3D5);
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DRM_WRITE8(info->mmio_map, 0x3D5, temp | 0x20);
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/* Enable MMIO */
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DRM_WRITE8(info->mmio_map, 0x3D4, 0x39);
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temp = DRM_READ8(info->mmio_map, 0x3D5);
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DRM_WRITE8(info->mmio_map, 0x3D5, temp | 0x01);
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/* Protect registers */
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OUT3C5B(info->mmio_map, 0x11, protect);
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}
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static inline void xgi_disable_mmio(struct xgi_info * info)
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{
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u8 protect = 0;
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u8 temp;
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/* Unprotect registers */
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DRM_WRITE8(info->mmio_map, 0x3C4, 0x11);
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protect = DRM_READ8(info->mmio_map, 0x3C5);
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DRM_WRITE8(info->mmio_map, 0x3C5, 0x92);
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/* Disable MMIO access */
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DRM_WRITE8(info->mmio_map, 0x3D4, 0x39);
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temp = DRM_READ8(info->mmio_map, 0x3D5);
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DRM_WRITE8(info->mmio_map, 0x3D5, temp & 0xFE);
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/* Protect registers */
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OUT3C5B(info->mmio_map, 0x11, protect);
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}
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static inline void xgi_enable_ge(struct xgi_info * info)
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{
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unsigned char bOld3cf2a = 0;
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int wait = 0;
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// Enable GE
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DRM_WRITE16(info->mmio_map, 0x3C4, 0x9211);
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// Save and close dynamic gating
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bOld3cf2a = IN3CFB(info->mmio_map, 0x2a);
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OUT3CFB(info->mmio_map, 0x2a, bOld3cf2a & 0xfe);
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// Reset both 3D and 2D engine
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OUT3X5B(info->mmio_map, 0x36, 0x84);
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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OUT3X5B(info->mmio_map, 0x36, 0x94);
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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OUT3X5B(info->mmio_map, 0x36, 0x84);
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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// Enable 2D engine only
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OUT3X5B(info->mmio_map, 0x36, 0x80);
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// Enable 2D+3D engine
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OUT3X5B(info->mmio_map, 0x36, 0x84);
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// Restore dynamic gating
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OUT3CFB(info->mmio_map, 0x2a, bOld3cf2a);
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}
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static inline void xgi_disable_ge(struct xgi_info * info)
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{
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int wait = 0;
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// Reset both 3D and 2D engine
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OUT3X5B(info->mmio_map, 0x36, 0x84);
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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OUT3X5B(info->mmio_map, 0x36, 0x94);
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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OUT3X5B(info->mmio_map, 0x36, 0x84);
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wait = 10;
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while (wait--) {
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DRM_READ8(info->mmio_map, 0x36);
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}
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// Disable 2D engine only
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OUT3X5B(info->mmio_map, 0x36, 0);
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}
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static inline void xgi_enable_dvi_interrupt(struct xgi_info * info)
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{
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OUT3CFB(info->mmio_map, 0x39, IN3CFB(info->mmio_map, 0x39) & ~0x01); //Set 3cf.39 bit 0 to 0
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OUT3CFB(info->mmio_map, 0x39, IN3CFB(info->mmio_map, 0x39) | 0x01); //Set 3cf.39 bit 0 to 1
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OUT3CFB(info->mmio_map, 0x39, IN3CFB(info->mmio_map, 0x39) | 0x02);
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}
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static inline void xgi_disable_dvi_interrupt(struct xgi_info * info)
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{
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OUT3CFB(info->mmio_map, 0x39, IN3CFB(info->mmio_map, 0x39) & ~0x02);
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}
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static inline void xgi_enable_crt1_interrupt(struct xgi_info * info)
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{
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OUT3CFB(info->mmio_map, 0x3d, IN3CFB(info->mmio_map, 0x3d) | 0x04);
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OUT3CFB(info->mmio_map, 0x3d, IN3CFB(info->mmio_map, 0x3d) & ~0x04);
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OUT3CFB(info->mmio_map, 0x3d, IN3CFB(info->mmio_map, 0x3d) | 0x08);
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}
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static inline void xgi_disable_crt1_interrupt(struct xgi_info * info)
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{
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OUT3CFB(info->mmio_map, 0x3d, IN3CFB(info->mmio_map, 0x3d) & ~0x08);
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}
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#endif
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