590 lines
18 KiB
C
590 lines
18 KiB
C
/*
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* Copyright 2007 Jérôme Glisse
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* Copyright 2007 Alex Deucher
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* Copyright 2007 Dave Airlie
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation on the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
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* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "radeon_ms.h"
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static int radeon_ms_gpu_address_space_init(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_state *state = &dev_priv->driver_state;
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/* initialize gpu mapping */
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dev_priv->gpu_vram_start = dev_priv->vram.offset;
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dev_priv->gpu_vram_end = dev_priv->gpu_vram_start + dev_priv->vram.size;
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/* align it on 16Mo boundary (clamp memory which is then
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* unreachable but not manufacturer should use strange
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* memory size */
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dev_priv->gpu_vram_end = dev_priv->gpu_vram_end & (~0xFFFFFF);
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dev_priv->gpu_vram_end -= 1;
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dev_priv->gpu_vram_size = dev_priv->gpu_vram_end -
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dev_priv->gpu_vram_start + 1;
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/* set gart size to 32Mo FIXME: should make a parameter for this */
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dev_priv->gpu_gart_size = 1024 * 1024 * 32;
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if (dev_priv->gpu_gart_size > (0xffffffffU - dev_priv->gpu_vram_end)) {
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/* align gart start to next 4Ko in gpu address space */
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dev_priv->gpu_gart_start = (dev_priv->gpu_vram_end + 1) + 0xfff;
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dev_priv->gpu_gart_start = dev_priv->gpu_gart_start & (~0xfff);
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dev_priv->gpu_gart_end = dev_priv->gpu_gart_start +
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dev_priv->gpu_gart_size;
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dev_priv->gpu_gart_end = (dev_priv->gpu_gart_end & (~0xfff)) -
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0x1000;
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} else {
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/* align gart start to next 4Ko in gpu address space */
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dev_priv->gpu_gart_start = (dev_priv->gpu_vram_start & ~0xfff) -
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dev_priv->gpu_gart_size;
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dev_priv->gpu_gart_start = dev_priv->gpu_gart_start & (~0xfff);
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dev_priv->gpu_gart_end = dev_priv->gpu_gart_start +
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dev_priv->gpu_gart_size;
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dev_priv->gpu_gart_end = (dev_priv->gpu_gart_end & (~0xfff)) -
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0x1000;
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}
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state->mc_fb_location =
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REG_S(MC_FB_LOCATION, MC_FB_START,
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dev_priv->gpu_vram_start >> 16) |
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REG_S(MC_FB_LOCATION, MC_FB_TOP, dev_priv->gpu_vram_end >> 16);
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state->display_base_addr =
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REG_S(DISPLAY_BASE_ADDR, DISPLAY_BASE_ADDR,
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dev_priv->gpu_vram_start);
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state->config_aper_0_base = dev_priv->gpu_vram_start;
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state->config_aper_1_base = dev_priv->gpu_vram_start;
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state->config_aper_size = dev_priv->gpu_vram_size;
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DRM_INFO("[radeon_ms] gpu vram start 0x%08X\n",
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dev_priv->gpu_vram_start);
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DRM_INFO("[radeon_ms] gpu vram end 0x%08X\n",
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dev_priv->gpu_vram_end);
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DRM_INFO("[radeon_ms] gpu gart start 0x%08X\n",
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dev_priv->gpu_gart_start);
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DRM_INFO("[radeon_ms] gpu gart end 0x%08X\n",
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dev_priv->gpu_gart_end);
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return 0;
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}
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static void radeon_ms_gpu_reset(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset;
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uint32_t reset_mask, host_path_cntl, cache_mode;
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radeon_ms_cp_stop(dev);
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radeon_ms_gpu_flush(dev);
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/* reset clock */
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clock_cntl_index = MMIO_R(CLOCK_CNTL_INDEX);
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pll_index_errata(dev_priv);
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mclk_cntl = PPLL_R(MCLK_CNTL);
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PPLL_W(MCLK_CNTL,
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mclk_cntl |
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MCLK_CNTL__FORCE_MCLKA |
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MCLK_CNTL__FORCE_MCLKB |
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MCLK_CNTL__FORCE_YCLKA |
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MCLK_CNTL__FORCE_YCLKB |
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MCLK_CNTL__FORCE_MC |
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MCLK_CNTL__FORCE_AIC);
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PPLL_W(SCLK_CNTL,
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PPLL_R(SCLK_CNTL) |
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SCLK_CNTL__FORCE_CP |
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SCLK_CNTL__FORCE_VIP);
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/* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
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* unexpected behaviour on some machines. Here we use
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* RADEON_HOST_PATH_CNTL to reset it.
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*/
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host_path_cntl = MMIO_R(HOST_PATH_CNTL);
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rbbm_soft_reset = MMIO_R(RBBM_SOFT_RESET);
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reset_mask = RBBM_SOFT_RESET__SOFT_RESET_CP |
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RBBM_SOFT_RESET__SOFT_RESET_HI |
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RBBM_SOFT_RESET__SOFT_RESET_VAP |
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RBBM_SOFT_RESET__SOFT_RESET_SE |
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RBBM_SOFT_RESET__SOFT_RESET_RE |
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RBBM_SOFT_RESET__SOFT_RESET_PP |
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RBBM_SOFT_RESET__SOFT_RESET_E2 |
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RBBM_SOFT_RESET__SOFT_RESET_RB;
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MMIO_W(RBBM_SOFT_RESET, rbbm_soft_reset | reset_mask);
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MMIO_R(RBBM_SOFT_RESET);
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MMIO_W(RBBM_SOFT_RESET, 0);
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MMIO_R(RBBM_SOFT_RESET);
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cache_mode = MMIO_R(RB2D_DSTCACHE_MODE);
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MMIO_W(RB2D_DSTCACHE_MODE,
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cache_mode | RB2D_DSTCACHE_MODE__DC_DISABLE_IGNORE_PE);
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MMIO_W(HOST_PATH_CNTL, host_path_cntl | HOST_PATH_CNTL__HDP_SOFT_RESET);
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MMIO_R(HOST_PATH_CNTL);
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MMIO_W(HOST_PATH_CNTL, host_path_cntl);
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MMIO_R(HOST_PATH_CNTL);
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MMIO_W(CLOCK_CNTL_INDEX, clock_cntl_index);
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pll_index_errata(dev_priv);
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PPLL_W(MCLK_CNTL, mclk_cntl);
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}
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static void radeon_ms_gpu_resume(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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uint32_t a;
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uint32_t i;
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/* make sure we have sane offset before restoring crtc */
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a = (MMIO_R(MC_FB_LOCATION) & MC_FB_LOCATION__MC_FB_START__MASK) << 16;
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MMIO_W(DISPLAY_BASE_ADDR, a);
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MMIO_W(CRTC2_DISPLAY_BASE_ADDR, a);
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MMIO_W(CRTC_OFFSET, 0);
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MMIO_W(CUR_OFFSET, 0);
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MMIO_W(CRTC_OFFSET_CNTL, CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL);
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MMIO_W(CRTC2_OFFSET, 0);
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MMIO_W(CUR2_OFFSET, 0);
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MMIO_W(CRTC2_OFFSET_CNTL, CRTC2_OFFSET_CNTL__CRTC2_OFFSET_FLIP_CNTL);
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for (i = 0; i < dev_priv->usec_timeout; i++) {
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if (!(CRTC_OFFSET__CRTC_GUI_TRIG_OFFSET &
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MMIO_R(CRTC_OFFSET))) {
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break;
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}
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DRM_UDELAY(1);
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}
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if (i >= dev_priv->usec_timeout) {
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DRM_ERROR("[radeon_ms] timeout waiting for crtc...\n");
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}
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for (i = 0; i < dev_priv->usec_timeout; i++) {
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if (!(CRTC2_OFFSET__CRTC2_GUI_TRIG_OFFSET &
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MMIO_R(CRTC2_OFFSET))) {
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break;
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}
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DRM_UDELAY(1);
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}
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if (i >= dev_priv->usec_timeout) {
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DRM_ERROR("[radeon_ms] timeout waiting for crtc...\n");
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}
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DRM_UDELAY(10000);
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}
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static void radeon_ms_gpu_stop(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl;
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uint32_t crtc2_gen_cntl, i;
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radeon_ms_wait_for_idle(dev);
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/* Capture MC_STATUS in case things go wrong ... */
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ov0_scale_cntl = dev_priv->ov0_scale_cntl = MMIO_R(OV0_SCALE_CNTL);
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crtc_ext_cntl = dev_priv->crtc_ext_cntl = MMIO_R(CRTC_EXT_CNTL);
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crtc_gen_cntl = dev_priv->crtc_gen_cntl = MMIO_R(CRTC_GEN_CNTL);
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crtc2_gen_cntl = dev_priv->crtc2_gen_cntl = MMIO_R(CRTC2_GEN_CNTL);
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ov0_scale_cntl &= ~OV0_SCALE_CNTL__OV0_OVERLAY_EN__MASK;
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crtc_ext_cntl |= CRTC_EXT_CNTL__CRTC_DISPLAY_DIS;
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crtc_gen_cntl &= ~CRTC_GEN_CNTL__CRTC_CUR_EN;
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crtc_gen_cntl &= ~CRTC_GEN_CNTL__CRTC_ICON_EN;
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crtc_gen_cntl |= CRTC_GEN_CNTL__CRTC_EXT_DISP_EN;
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crtc_gen_cntl |= CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B;
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crtc2_gen_cntl &= ~CRTC2_GEN_CNTL__CRTC2_CUR_EN;
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crtc2_gen_cntl &= ~CRTC2_GEN_CNTL__CRTC2_ICON_EN;
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crtc2_gen_cntl |= CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B;
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MMIO_W(OV0_SCALE_CNTL, ov0_scale_cntl);
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MMIO_W(CRTC_EXT_CNTL, crtc_ext_cntl);
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MMIO_W(CRTC_GEN_CNTL, crtc_gen_cntl);
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MMIO_W(CRTC2_GEN_CNTL, crtc2_gen_cntl);
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DRM_UDELAY(10000);
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switch (dev_priv->family) {
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case CHIP_R100:
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case CHIP_R200:
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case CHIP_RV200:
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case CHIP_RV250:
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case CHIP_RV280:
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case CHIP_RS300:
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for (i = 0; i < dev_priv->usec_timeout; i++) {
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if ((MC_STATUS__MC_IDLE & MMIO_R(MC_STATUS))) {
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DRM_INFO("[radeon_ms] gpu stoped in %d usecs\n",
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i);
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return;
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}
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DRM_UDELAY(1);
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}
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break;
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case CHIP_R300:
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case CHIP_R350:
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case CHIP_R360:
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case CHIP_RV350:
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case CHIP_RV370:
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case CHIP_RV380:
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case CHIP_RS400:
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case CHIP_RV410:
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case CHIP_R420:
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case CHIP_R430:
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case CHIP_R480:
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for (i = 0; i < dev_priv->usec_timeout; i++) {
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if ((MC_STATUS__MC_IDLE_R3 & MMIO_R(MC_STATUS))) {
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DRM_INFO("[radeon_ms] gpu stoped in %d usecs\n",
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i);
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return;
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}
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DRM_UDELAY(1);
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}
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break;
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default:
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DRM_ERROR("Unknown radeon family, aborting\n");
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return;
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}
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DRM_ERROR("[radeon_ms] failed to stop gpu...will proceed anyway\n");
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DRM_UDELAY(20000);
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}
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static int radeon_ms_wait_for_fifo(struct drm_device *dev, int num_fifo)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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int i;
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for (i = 0; i < dev_priv->usec_timeout; i++) {
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int t;
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t = RBBM_STATUS__CMDFIFO_AVAIL__MASK & MMIO_R(RBBM_STATUS);
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t = t >> RBBM_STATUS__CMDFIFO_AVAIL__SHIFT;
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if (t >= num_fifo)
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return 0;
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DRM_UDELAY(1);
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}
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DRM_ERROR("[radeon_ms] failed to wait for fifo\n");
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return -EBUSY;
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}
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int radeon_ms_gpu_initialize(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_state *state = &dev_priv->driver_state;
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int ret;
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state->disp_misc_cntl = DISP_MISC_CNTL__SYNC_PAD_FLOP_EN |
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REG_S(DISP_MISC_CNTL, SYNC_STRENGTH, 2) |
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REG_S(DISP_MISC_CNTL, PALETTE_MEM_RD_MARGIN, 0xb) |
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REG_S(DISP_MISC_CNTL, PALETTE2_MEM_RD_MARGIN, 0xb) |
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REG_S(DISP_MISC_CNTL, RMX_BUF_MEM_RD_MARGIN, 0x5);
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state->disp_merge_cntl = REG_S(DISP_MERGE_CNTL, DISP_GRPH_ALPHA, 0xff) |
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REG_S(DISP_MERGE_CNTL, DISP_OV0_ALPHA, 0xff);
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state->disp_pwr_man = DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN |
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DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN |
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REG_S(DISP_PWR_MAN, DISP_PWR_MAN_DPMS, DISP_PWR_MAN_DPMS__OFF) |
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DISP_PWR_MAN__DISP_D3_RST |
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DISP_PWR_MAN__DISP_D3_REG_RST |
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DISP_PWR_MAN__DISP_D3_GRPH_RST |
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DISP_PWR_MAN__DISP_D3_SUBPIC_RST |
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DISP_PWR_MAN__DISP_D3_OV0_RST |
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DISP_PWR_MAN__DISP_D1D2_GRPH_RST |
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DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST |
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DISP_PWR_MAN__DISP_D1D2_OV0_RST |
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DISP_PWR_MAN__DISP_DVO_ENABLE_RST |
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DISP_PWR_MAN__TV_ENABLE_RST;
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state->disp2_merge_cntl = 0;
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ret = radeon_ms_gpu_address_space_init(dev);
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if (ret) {
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return ret;
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}
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/* initialize bus */
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ret = dev_priv->bus_init(dev);
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if (ret != 0) {
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return ret;
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}
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return 0;
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}
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void radeon_ms_gpu_dpms(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct radeon_state *state = &dev_priv->driver_state;
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if (dev_priv->crtc1_dpms == dev_priv->crtc2_dpms) {
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/* both crtc are in same state so use global display pwr */
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state->disp_pwr_man &= ~DISP_PWR_MAN__DISP_PWR_MAN_DPMS__MASK;
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switch(dev_priv->crtc1_dpms) {
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case DPMSModeOn:
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state->disp_pwr_man |= REG_S(DISP_PWR_MAN,
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DISP_PWR_MAN_DPMS,
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DISP_PWR_MAN_DPMS__ON);
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break;
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case DPMSModeStandby:
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state->disp_pwr_man |= REG_S(DISP_PWR_MAN,
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DISP_PWR_MAN_DPMS,
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DISP_PWR_MAN_DPMS__STANDBY);
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break;
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case DPMSModeSuspend:
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state->disp_pwr_man |= REG_S(DISP_PWR_MAN,
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DISP_PWR_MAN_DPMS,
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DISP_PWR_MAN_DPMS__SUSPEND);
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break;
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case DPMSModeOff:
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state->disp_pwr_man |= REG_S(DISP_PWR_MAN,
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DISP_PWR_MAN_DPMS,
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DISP_PWR_MAN_DPMS__OFF);
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break;
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default:
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/* error */
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break;
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}
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MMIO_W(DISP_PWR_MAN, state->disp_pwr_man);
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} else {
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state->disp_pwr_man &= ~DISP_PWR_MAN__DISP_PWR_MAN_DPMS__MASK;
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state->disp_pwr_man |= REG_S(DISP_PWR_MAN,
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DISP_PWR_MAN_DPMS,
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DISP_PWR_MAN_DPMS__ON);
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MMIO_W(DISP_PWR_MAN, state->disp_pwr_man);
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}
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}
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void radeon_ms_gpu_flush(struct drm_device *dev)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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uint32_t i;
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uint32_t purge2d;
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uint32_t purge3d;
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switch (dev_priv->family) {
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case CHIP_R100:
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case CHIP_R200:
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case CHIP_RV200:
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case CHIP_RV250:
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case CHIP_RV280:
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case CHIP_RS300:
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purge2d = REG_S(RB2D_DSTCACHE_CTLSTAT, DC_FLUSH, 3) |
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REG_S(RB2D_DSTCACHE_CTLSTAT, DC_FREE, 3);
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purge3d = REG_S(RB3D_DSTCACHE_CTLSTAT, DC_FLUSH, 3) |
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REG_S(RB3D_DSTCACHE_CTLSTAT, DC_FREE, 3);
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MMIO_W(RB2D_DSTCACHE_CTLSTAT, purge2d);
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MMIO_W(RB3D_DSTCACHE_CTLSTAT, purge3d);
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break;
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case CHIP_R300:
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case CHIP_R350:
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case CHIP_R360:
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case CHIP_RV350:
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case CHIP_RV370:
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case CHIP_RV380:
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case CHIP_RS400:
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case CHIP_RV410:
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case CHIP_R420:
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case CHIP_R430:
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case CHIP_R480:
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purge2d = REG_S(RB2D_DSTCACHE_CTLSTAT, DC_FLUSH, 3) |
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REG_S(RB2D_DSTCACHE_CTLSTAT, DC_FREE, 3);
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purge3d = REG_S(RB3D_DSTCACHE_CTLSTAT_R3, DC_FLUSH, 3) |
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REG_S(RB3D_DSTCACHE_CTLSTAT_R3, DC_FREE, 3);
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MMIO_W(RB2D_DSTCACHE_CTLSTAT, purge2d);
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MMIO_W(RB3D_DSTCACHE_CTLSTAT_R3, purge3d);
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break;
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default:
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|
DRM_ERROR("Unknown radeon family, aborting\n");
|
|
return;
|
|
}
|
|
for (i = 0; i < dev_priv->usec_timeout; i++) {
|
|
if (!(RB2D_DSTCACHE_CTLSTAT__DC_BUSY &
|
|
MMIO_R(RB2D_DSTCACHE_CTLSTAT))) {
|
|
return;
|
|
}
|
|
DRM_UDELAY(1);
|
|
}
|
|
DRM_ERROR("[radeon_ms] gpu flush timeout\n");
|
|
}
|
|
|
|
void radeon_ms_gpu_restore(struct drm_device *dev, struct radeon_state *state)
|
|
{
|
|
struct drm_radeon_private *dev_priv = dev->dev_private;
|
|
uint32_t wait_until;
|
|
uint32_t fbstart;
|
|
int ret, ok = 1;
|
|
|
|
radeon_ms_gpu_reset(dev);
|
|
radeon_ms_wait_for_idle(dev);
|
|
radeon_ms_gpu_stop(dev);
|
|
|
|
MMIO_W(AIC_CTRL, state->aic_ctrl);
|
|
MMIO_W(MC_FB_LOCATION, state->mc_fb_location);
|
|
MMIO_R(MC_FB_LOCATION);
|
|
MMIO_W(CONFIG_APER_0_BASE, state->config_aper_0_base);
|
|
MMIO_W(CONFIG_APER_1_BASE, state->config_aper_1_base);
|
|
MMIO_W(CONFIG_APER_SIZE, state->config_aper_size);
|
|
MMIO_W(DISPLAY_BASE_ADDR, state->display_base_addr);
|
|
if (dev_priv->bus_restore) {
|
|
dev_priv->bus_restore(dev, state);
|
|
}
|
|
|
|
radeon_ms_gpu_reset(dev);
|
|
radeon_ms_gpu_resume(dev);
|
|
|
|
MMIO_W(BUS_CNTL, state->bus_cntl);
|
|
wait_until = WAIT_UNTIL__WAIT_DMA_VIPH0_IDLE |
|
|
WAIT_UNTIL__WAIT_DMA_VIPH1_IDLE |
|
|
WAIT_UNTIL__WAIT_DMA_VIPH2_IDLE |
|
|
WAIT_UNTIL__WAIT_DMA_VIPH3_IDLE |
|
|
WAIT_UNTIL__WAIT_DMA_VID_IDLE |
|
|
WAIT_UNTIL__WAIT_DMA_GUI_IDLE |
|
|
WAIT_UNTIL__WAIT_2D_IDLE |
|
|
WAIT_UNTIL__WAIT_3D_IDLE |
|
|
WAIT_UNTIL__WAIT_2D_IDLECLEAN |
|
|
WAIT_UNTIL__WAIT_3D_IDLECLEAN |
|
|
WAIT_UNTIL__WAIT_HOST_IDLECLEAN;
|
|
switch (dev_priv->family) {
|
|
case CHIP_R100:
|
|
case CHIP_R200:
|
|
case CHIP_RV200:
|
|
case CHIP_RV250:
|
|
case CHIP_RV280:
|
|
case CHIP_RS300:
|
|
break;
|
|
case CHIP_R300:
|
|
case CHIP_R350:
|
|
case CHIP_R360:
|
|
case CHIP_RV350:
|
|
case CHIP_RV370:
|
|
case CHIP_RV380:
|
|
case CHIP_RS400:
|
|
case CHIP_RV410:
|
|
case CHIP_R420:
|
|
case CHIP_R430:
|
|
case CHIP_R480:
|
|
wait_until |= WAIT_UNTIL__WAIT_VAP_IDLE;
|
|
break;
|
|
}
|
|
MMIO_W(WAIT_UNTIL, wait_until);
|
|
MMIO_W(DISP_MISC_CNTL, state->disp_misc_cntl);
|
|
MMIO_W(DISP_PWR_MAN, state->disp_pwr_man);
|
|
MMIO_W(DISP_MERGE_CNTL, state->disp_merge_cntl);
|
|
MMIO_W(DISP_OUTPUT_CNTL, state->disp_output_cntl);
|
|
MMIO_W(DISP2_MERGE_CNTL, state->disp2_merge_cntl);
|
|
|
|
/* Setup engine location. This shouldn't be necessary since we
|
|
* set them appropriately before any accel ops, but let's avoid
|
|
* random bogus DMA in case we inadvertently trigger the engine
|
|
* in the wrong place (happened).
|
|
*/
|
|
ret = radeon_ms_wait_for_fifo(dev, 2);
|
|
if (ret) {
|
|
ok = 0;
|
|
DRM_ERROR("[radeon_ms] no fifo for setting up dst & src gui\n");
|
|
DRM_ERROR("[radeon_ms] proceed anyway\n");
|
|
}
|
|
fbstart = (MC_FB_LOCATION__MC_FB_START__MASK &
|
|
MMIO_R(MC_FB_LOCATION)) << 16;
|
|
MMIO_W(DST_PITCH_OFFSET,
|
|
REG_S(DST_PITCH_OFFSET, DST_OFFSET, fbstart >> 10));
|
|
MMIO_W(SRC_PITCH_OFFSET,
|
|
REG_S(SRC_PITCH_OFFSET, SRC_OFFSET, fbstart >> 10));
|
|
|
|
ret = radeon_ms_wait_for_fifo(dev, 1);
|
|
if (ret) {
|
|
ok = 0;
|
|
DRM_ERROR("[radeon_ms] no fifo for setting up dp data type\n");
|
|
DRM_ERROR("[radeon_ms] proceed anyway\n");
|
|
}
|
|
#ifdef __BIG_ENDIAN
|
|
MMIO_W(DP_DATATYPE, DP_DATATYPE__DP_BYTE_PIX_ORDER);
|
|
#else
|
|
MMIO_W(DP_DATATYPE, 0);
|
|
#endif
|
|
|
|
ret = radeon_ms_wait_for_fifo(dev, 1);
|
|
if (ret) {
|
|
ok = 0;
|
|
DRM_ERROR("[radeon_ms] no fifo for setting up surface cntl\n");
|
|
DRM_ERROR("[radeon_ms] proceed anyway\n");
|
|
}
|
|
MMIO_W(SURFACE_CNTL, SURFACE_CNTL__SURF_TRANSLATION_DIS);
|
|
|
|
ret = radeon_ms_wait_for_fifo(dev, 2);
|
|
if (ret) {
|
|
ok = 0;
|
|
DRM_ERROR("[radeon_ms] no fifo for setting scissor\n");
|
|
DRM_ERROR("[radeon_ms] proceed anyway\n");
|
|
}
|
|
MMIO_W(DEFAULT_SC_BOTTOM_RIGHT, 0x1fff1fff);
|
|
MMIO_W(DEFAULT2_SC_BOTTOM_RIGHT, 0x1fff1fff);
|
|
|
|
ret = radeon_ms_wait_for_fifo(dev, 1);
|
|
if (ret) {
|
|
ok = 0;
|
|
DRM_ERROR("[radeon_ms] no fifo for setting up gui cntl\n");
|
|
DRM_ERROR("[radeon_ms] proceed anyway\n");
|
|
}
|
|
MMIO_W(DP_GUI_MASTER_CNTL, 0);
|
|
|
|
ret = radeon_ms_wait_for_fifo(dev, 5);
|
|
if (ret) {
|
|
ok = 0;
|
|
DRM_ERROR("[radeon_ms] no fifo for setting up clear color\n");
|
|
DRM_ERROR("[radeon_ms] proceed anyway\n");
|
|
}
|
|
MMIO_W(DP_BRUSH_BKGD_CLR, 0x00000000);
|
|
MMIO_W(DP_BRUSH_FRGD_CLR, 0xffffffff);
|
|
MMIO_W(DP_SRC_BKGD_CLR, 0x00000000);
|
|
MMIO_W(DP_SRC_FRGD_CLR, 0xffffffff);
|
|
MMIO_W(DP_WRITE_MSK, 0xffffffff);
|
|
|
|
if (!ok) {
|
|
DRM_ERROR("[radeon_ms] engine restore not enough fifo\n");
|
|
}
|
|
}
|
|
|
|
void radeon_ms_gpu_save(struct drm_device *dev, struct radeon_state *state)
|
|
{
|
|
struct drm_radeon_private *dev_priv = dev->dev_private;
|
|
|
|
state->aic_ctrl = MMIO_R(AIC_CTRL);
|
|
state->bus_cntl = MMIO_R(BUS_CNTL);
|
|
state->mc_fb_location = MMIO_R(MC_FB_LOCATION);
|
|
state->display_base_addr = MMIO_R(DISPLAY_BASE_ADDR);
|
|
state->config_aper_0_base = MMIO_R(CONFIG_APER_0_BASE);
|
|
state->config_aper_1_base = MMIO_R(CONFIG_APER_1_BASE);
|
|
state->config_aper_size = MMIO_R(CONFIG_APER_SIZE);
|
|
state->disp_misc_cntl = MMIO_R(DISP_MISC_CNTL);
|
|
state->disp_pwr_man = MMIO_R(DISP_PWR_MAN);
|
|
state->disp_merge_cntl = MMIO_R(DISP_MERGE_CNTL);
|
|
state->disp_output_cntl = MMIO_R(DISP_OUTPUT_CNTL);
|
|
state->disp2_merge_cntl = MMIO_R(DISP2_MERGE_CNTL);
|
|
if (dev_priv->bus_save) {
|
|
dev_priv->bus_save(dev, state);
|
|
}
|
|
}
|
|
|
|
int radeon_ms_wait_for_idle(struct drm_device *dev)
|
|
{
|
|
struct drm_radeon_private *dev_priv = dev->dev_private;
|
|
int i, j, ret;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
ret = radeon_ms_wait_for_fifo(dev, 64);
|
|
if (ret) {
|
|
DRM_ERROR("[radeon_ms] fifo not empty\n");
|
|
}
|
|
for (j = 0; j < dev_priv->usec_timeout; j++) {
|
|
if (!(RBBM_STATUS__GUI_ACTIVE & MMIO_R(RBBM_STATUS))) {
|
|
radeon_ms_gpu_flush(dev);
|
|
return 0;
|
|
}
|
|
DRM_UDELAY(1);
|
|
}
|
|
DRM_ERROR("[radeon_ms] idle timed out: status=0x%08x\n",
|
|
MMIO_R(RBBM_STATUS));
|
|
radeon_ms_gpu_stop(dev);
|
|
radeon_ms_gpu_reset(dev);
|
|
}
|
|
return -EBUSY;
|
|
}
|